Generate statement usage verilog

[gangireddy.p]

Hi,
Can I use generate block for array of instances. Like in the below way

wire [4:0] in1;
wire [3:0] in2;

wire [4:0] sig1;
wire [3:0] sig2[0:4];

generate for(i=0;i<5;i=i+1)
begin
assign sig1 = in1;
assign sig2 = in2;
end
endgenerate

While running simulation in dve, the sig1 is toggling but the sig2 is not assigned properly. Is it because like in generate block we cannot assign to a bus or any other thing. Please let me know.

 

[bharat_in]

Hey,
I tried running your stuff as below, i don't see any problem.
Output is also shown below.
Please, post your testbench. May be something is wrong with the testbench.

module gen_chk(in1,in2, sig1,sig2);
input  [4:0] in1;
input  [3:0] in2;

output [4:0] sig1;
output [3:0] sig2 [4:0];

genvar i;

generate
for(i=0;i<5;i=i+1)
begin:loop
  assign sig1[i] = in1[i];
  assign sig2[i] = in2;
end
endgenerate

endmodule

module gen_chk_tb();
reg [4:0] in1;
reg [3:0] in2;

reg [4:0] out1;
reg [3:0] out2[4:0];

 gen_chk gen_chkU(in1,in2,out1,out2);
 
 initial 
 begin
 in1 = 5'h00;
 in2 =4'h0;
 #10;
 in1 = 5'h01;
 in2 =4'h1;
 #10;
 in1 = 5'h02;
 in2=4'h0;
 #10;
 in1 = 5'h03;
 in2=4'h1;
 #10;
 in1 = 5'h04;
 in2=4'h0;
 
 end

initial
  begin
      $monitor("Time %t, sig1 = %d,sig2[0] = %d,sig2[1] = %d,sig2[2] = %d,sig2[3] = %d",$time,out1,out2[0],out2[1],out2[2],out2[3]);
  end
endmodule

Output
Time 0, sig1 = 0,sig2[0] = 0,sig2[1] = 0,sig2[2] = 0,sig2[3] = 0
Time 10, sig1 = 1,sig2[0] = 1,sig2[1] = 1,sig2[2] = 1,sig2[3] = 1
Time 20, sig1 = 2,sig2[0] = 0,sig2[1] = 0,sig2[2] = 0,sig2[3] = 0
Time 30, sig1 = 3,sig2[0] = 1,sig2[1] = 1,sig2[2] = 1,sig2[3] = 1
Time 40, sig1 = 4,sig2[0] = 0,sig2[1] = 0,sig2[2] = 0,sig2[3] = 0

 

[ljxpjpjljx]

I think the answer is correct!