generate signal assignment in vhdl

[ali.329]

I have a question. I want to use generate to signal assignment. but simulator takes me an error. the error is :

" Illegal target for signal assignment."

and

"Unknown identifier A0_i."

also i don't permit to change signal name.

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Code VHDL - [expand]
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architecure sss of fff is
signal A0_0 : bit ;
signal A0_1 : bit ;
signal A0_2 : bit ;
signal A0_3 : bit ;
 
begin
      U0 : for i in 0 to 3 generate
      U1 : A0_i <= a(i) and b(i) ;
      end generate;
end sss;

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thanks.

 

[ThisIsNotSam]

why wouldn't you make an array and use i to index? if you absolutely need all 4 A0 signals, you can make a temp array, work on it, and then feed the original signals.

 

[FvM]

Generate can access array elements but doesn't perform text manipulations of signal names. Need to define a bit_vector port signal.

 

[ali.329]

Thanks a lot.
So there isn't any way to solve this problem with these signals name?
I must define array.

 

[ads-ee]

Thanks a lot.
So there isn't any way to solve this problem with these signals name?
I must define array.

You have already been told it's not possible, why does it need repeating?

VHDL is not a string manipulation language, and signal names are not strings that you can perform text manipulation on to construct new signal names. You can perhaps do this in some programing languages, but VHDL is less than a crummy programming language.

 

[vGoodtimes]

You can do it with a 3rd party pre-processor that generates a new file from a template. At one point I had one that let me embed python code in a VHDL/Verilog file for the purpose of code generation.

 

[FvM]

You can do it with a 3rd party pre-processor that generates a new file from a template. At one point I had one that let me embed python code in a VHDL/Verilog file for the purpose of code generation.

Yes, you can do that. But I presume the thread topic is learning valid VHDL syntax rather than using a non-portable method to solve a trivial coding problem.