generate random number in vhdl

[k_cheng_aun2000]

random number in vhdl

anyone know how to implement random number generator between -1 to 1 in VHDL using Quartus II software.

thanks

 

[jamesyang1209]

random number vhdl

In digital system, all data is 0 or 1.
Where is the source for seed of the random number generator?

We have tried using meta-stable to generate the seed.
You also can use RTC (real time clock) input, since each time the time input will be different.
For asic without RTC, you can think about other idea about how to generae the seed in digital system.

 

[hoangthanhtung]

I know the examples about your problem in www.xess.com site but I do not memory exactly link. It is written by VHDL with FPGA chip of Xilnx using Webpack, but I think you can research and change it to implement by Altera software. Good luck