Generate netlist from layout!!

[letan]

I am using Cadence for layout. I need generate netlist from layout to simulate. How to make a netlist input file to simulate? Please help me!!
Thanks.

 

[ianalog]

first, you must have the extract LIB . then, you may extract the netlist by diva or calibre. From the extracted layout we may get the netlist.

 

[letan]

Hi, ianalog!
Thank you for your replay, but:
What is command in layout to extract LIB and how to make to extract netlist by DIVA?
In layout(cadence)
Tools -> Simulation -> Other then
On the toolbar
Simulation -> Initialize to show Simulation Run Directory
then
Simulation -> Netlist/Simulate to extract netlist
but I can't.
I need extract netlist from layout to simulate layout after check DRC and LVS.

 

[waxtomato]

make a dummy netlist and run lvs; maybe you can get netlist from layout

 

[firegun]

Do you wanna run a post simulation to ensure that your layout could work correctly with the parasitical risistors or capacitors?Maybe you should use the LPE and PRE tools to get a full netlist for your simulation.

Send via mobile phone wap.edaboard.com

 

[DZC]

It seems depend on which Verifier you use.
As far as I know,such as DIVA,Assura and Calibre have different approaches.

 

[srieda]

make a dummy netlist and run lvs; maybe you can get netlist from layout

Good method.. but u cant get parasitics...