Pls give me an idea if there is a module which i need to instantiate in a generate for loop such as outputs of the first instant shall go as an input to the next instant.If u could show me by the help of a small example its shall be good.
Here's a simple 8-bit shift register created by generating eight "dflop" modules.
The nine "path" wires connect the chain of dflops, from first input through last output.
"count" simply generates a square-wave test signal, like a built-in test bench.
Code:
module top (clk, out);
input clk;
reg [3:0] count = 0;
wire [8:0] path;
output out;
always @ (posedge clk)
count <= count + 1;
assign path[0] = count[3];
assign out = path[8];
genvar n;
generate
for (n=0; n<=7; n=n+1) begin : flops
dflop u (.clk(clk), .in(path[n]), .out(path[n+1]));
end
endgenerate
endmodule
module dflop (clk, in, out);
input clk, in;
output reg out;
always @ (posedge clk)
out <= in;
endmodule
I've noticed Verilog-2001 module headers (inline port declaration + name) still causes problems with some tools. It's 6 years after Verilog-2001 was formally standardized, and a lot of low-end simulator/synthesis tools have impose limitations on Verilog-2001 syntax.
For example, Cadence Ambit/PKS5 doesn't like downward-ordered (Verilog-2001) generate loops. Here's a (silly) example:
Code:
// bad loop - won't synthesize properly in Xilinx XST 9.1i, or Cadence Buildgates
genvar g;
generate for ( x=7; x > 0; x=x-1 ) begin : bad_loop
if ( x == 7 )
assign my_signal[x] = my_input;
else
assign my_signal[x] = ^my_signal[7:x+1]; // composite-XOR
end
True. I've been lucky so far in that the tools I've used have been happy with Verilog 2001. I'm glad, because it does save some typing and makes things more readable.
Opps! Yes, I typed that example on the fly, so it wasn't a practical (*real*) example.
The true-testcase I had instantiated some instances inside the body of the generate/for loop. XST 9.1i and Cadence/PKS5 did NOT like the downward ordered loop. But when I changed the loop-order, the same file synthesized correctly.
Anyway, I've also had A\ltera's Qua\rtus-II 7.1 (web-edition) crash on me, when I declare signals inside a Systemverilog generate-block:
Code:
typedef enum int {
TARGET_A = 0,
TARGET_B = 1,
TARGET_C = 2
} et_target;
module haha #(
parameter et_target target = TARGET_A
) (
input logic [7:0] x,
input logic [7:0] y,
output logic [7:0] z
);
// yet ... another ... silly ... example ...
generate
if ( target == TARGET_A ) begin : gen_target_a
logic [7:0] x1, y1; // <-- sometimes causes
// A ltera Quartus-II 7.1 to crash!
assign x1 = ~x;
assign y1 = {y,y}>>1; // rotate-right 1-bit
assign z = x1 + y1;
end // : gen_target_a
if ( target == TARGET_B ) begin : gen_target_b
assign z = x + y;
end // : gen_target_a
endgenerate
endmodule // : haha
Now Quartus-II 7.1 doesn't crash consistently -- it really seems to depend on what else is in the design-hierarchy. But I did find out, moving the 'logic [7:0] x1, y1' declaration to *OUTSIDE* the generate-block always fixed the crashes.
Sorry again. Yes, that's Systemverilog. Altera Quartus-II 7.1 supports Verilog, Systemverilog, and VHDL synthesis. The Systemverilog support is primitive (lots of constructs aren't suppored yet), but I like using Quartus-II 7.1 web-edition as an excuse to practice Systemverilog.
Hi all,
I have a doubt in echo 47 code ..
in your code is generate/endgenerate needed? .. wont the for loop do the same job of calling the module mant times with different parameters..