Generate layout from schematic in Cadence

[justsunny]

Is there any way to generate layout from an existing schematic in cadence (using command or tools)?

Thanks.

 

[oermens]

virtuoso xl

 

[justsunny]

Could you please tell me the steps to do it in virtuso xl ? I am new to the analog IC and layout design.

Thanks in advance.

 

[diemilio]

Depends on the process you're using. If you are just designing a sample circuit using components from the basic libraries is going to be very complicated to do layout because you will have to define each of the mask layers, DRC and LVS rules yourself. Now, if you are using a specific process like AMI or TSMC and you have a PDK install, the process is quite straight forward. Are you using something like this?? Please try to give as much info as possible; is hard to tell you how to proceed if we don't know what you have available.

Regards,

diemilio

 

[shashikumar.22]

Virtuso layout XL is used to generate the layout from schematic, you can then either route it manually. well if you need the steps then follow this link, well you can also google down for the VXL tutorials if you need further information.

**broken link removed**

 

[dkace]

Correct responses, but this is only to estimate space!

You will have to mess with all transistors and devices to achieve good matching ...

After you pass LVS, XL will always be linked to your schematic, and this is a plus.

Or, you can define fingers, multiplicity etc from scematic and make your life easier!

D.

 

[bsc_user]

Hi,

When generating layout from schematic in Layout XL
I get only pins (no transistors)
What could be a problem?

I use NCSU EDA libraries (NCSU EDA Wiki - NCSU EDA Wiki).
Problem occurs for simple inverter case,
and when I go to Library Manager in Cadence,
and choose layout view for nmos and pmos they exist (i.e. layout editor shows these layouts)

Thanks in advance!

 

[muffassir]

Hi,,

first click on generate from all sources
then
u can press

shift f

to see urr MOSes

[REMOVED - MODERATOR]

 

[bsc_user]

Thanks for reply,

We used new version of Cadence IC package (IC61), new environment was a problem,
with previous version (IC5) works just fine!