44MHz ÷ 40Hz = 1 100 000
--> you need 1 100 000 pulses of 44MHz for one 40Hz pulse
Each pulse has two edges: thus 550 000 pulses of 44MHz from one 40Hz edge to the next.
Now use a 20 bit binary counter running from 44MHz.
Compare it with 549 999 (count from 0 to 549 999)
On compare match: toggle the 40Hz signal and synchronously reset the 20 bit counter.
Therefore in order to make 1100000 you need to know what the x is in 2^x.
On a side note, since I assume you're new to vhdl
Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
-- allows additionsignal s :unsigned(x-1downto0);
s <= s+1;-- does not allow additionsignal slv :std_logic_vector(x-1downto0);-- requires type conversion
slv <=std_logic_vector(unsigned(slv)+1);-- using variables allows addition to happen instantaneous which will help you around the edges ;)
A variable will also synthesizes to an adder following a register, so if your clock frequency is high and you use the output of this add operation for say a huge mux, some other large combinational logic, or has a lot of loads, you may not meet timing. The s output, if defined as a variable with the following assignment s := s+1;, will be a combinational output.
So yeah it might "help you around the edges" but there is a caveat.