Re: Generate 27 MHz clock from a 40 MHz input clock on a FPG
You can infer CLKDLL in Xilinx FPGA devices. CLKDV_DIVIDE is in integer value. You'll probably need a combination of CLKDLLs to create 27MHz. Therefore, it might be advisable to closer frequency. (40MHz/1.5 = 26.7MHz)
The following is the example from Xilinx manual. Hope that this helps.
CLKDLL CLKDLL_instance_name (.CLK0 (user_CLK0),
.CLK180 (user_CLK180),
.CLK270 (user_CLK270),
.CLK2X (user_CLK2X),
.CLK90 (user_CLK90),
.CLKDV (user_CLKDV),
.LOCKED (user_LOCKED),
.CLKFB (user_CLKFB),
.CLKIN (user_CLKIN),
.RST (user_RST));
defparam CLKDLL_instance_name.CLKDV_DIVIDE = integer_value;
//(1.5,2,2.5,3,4,5,8,16)
defparam CLKDLL_instance_name.DUTY_CYCLE_CORRECTION = boolean_value;//
(TRUE, FALSE)
defparam CLKDLL_instance_name.STARTUP_WAIT = boolean_value; // (TRUE,
FALSE)