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i tried this. maybe i have to tell you a little bit more about the background. we have a layout in c@dence ic5 and want to extract parasitic capacitances and resistances with star rxc from synopsys (not assura). therefore we need the lef/def-files from our design. so i choose export in file menu of ciw and provide my cell view. after i did this, i had the lef/def files, but when i tried to import it in star rxc there where a lot of errors.
it seem that ic5 only export the technology information (layer, via ... definition) and not the user gate information.
is there another way for translation? or do i have to change some properties?
in your case, you should pipo out the gds file and do full gds extraction for analog design. or run abstract first to get the std cell lef file first, and stay with def flow for std cell digital design.