clarify Clock enable & Gated Clock
As I know, in most ASIC libraries, the clock enable pin of a flip-flop is implemented by putting a MUX in front of the flip-flop D input, when CE is enabled, new data will be select, otherwise, Q will be wired to D, so the old data will be retained. So actually, Clock Enable has nothing to do with reducing the power. If you want save power, you should use clock gating techniques, which indeed disable the clock of the flip-flops. There are many ways to do so, but what ever you use, the following guidelines should be followed:
1. avoid clock glitch
2. avoid clip the clock active phase
3. reduce the impact on DFT coverage
More details, please refer to synopsys power products manuals, like "Power Compiler User's Manual".