Nov 24, 2015 #1 ivlsi Advanced Member level 3 Joined Feb 17, 2012 Messages 883 Helped 17 Reputation 32 Reaction score 16 Trophy points 1,298 Activity points 6,868 Hi All, How should I implement a Gated Clock in Altera devices? Is there some specific cell, which I should use? Thank you
Hi All, How should I implement a Gated Clock in Altera devices? Is there some specific cell, which I should use? Thank you
Nov 24, 2015 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,411 Helped 14,749 Reputation 29,780 Reaction score 14,096 Trophy points 1,393 Location Bochum, Germany Activity points 298,058 Depending on the used FPGA family, a CLKCTRL block might do what you want. It's rather unusual to have gated clocks in FPGA designs.
Depending on the used FPGA family, a CLKCTRL block might do what you want. It's rather unusual to have gated clocks in FPGA designs.
Nov 24, 2015 #3 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 Why do you want one? whats wrong with a normal clock?
Nov 24, 2015 #4 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,822 Reputation 3,654 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,207 And why doesn't using a clock enable work? If you are trying to save power then using an FPGA is the primary problem.
And why doesn't using a clock enable work? If you are trying to save power then using an FPGA is the primary problem.