Gate level simulation: Quaries on simulation issues

[vln2k6]

Dear experts,
While doing post synthesis simulation i am having the error such that it is not able to find the library file paths.
I have complied the library files for the virtex2vp_7 and placed in "D:\xilinx\verilog\src\simprims"

I have given this path in the vsim command options in the xilinx but i am unable to load the design.

 

[satyakumar]

Hi,
Gate level simulation can be done in NCSIM for xilinx syn platform, u need netlist file generated by xilinx and design libraries like simprim and unisim etc(which should be compiled in NCSIM), testbench file, and sdf file.

 

[vln2k6]

I have gnerated the netlist and loaded it in modelsim by invocking from xilinx post translate simulation.
I need to use now testbench could u give me how to load the testbench...for the post translate simulation.
How to generate the test bench file for the post synthesis simulation.
Do i need to give some options in xilinx tool.

Thank You

 

[cnspy]

I do not think you can generate test bench by tool. You have to write it by yourself.

 

[sam3001]

As far as i know synaptic CAD can be used to generate testbench though I did not test