gate level simulation issue

[richardhuang]

when i do gate level simulation, i encountered an issue, the memory output is "x",and how can i initialize it. although i can force the output, but the release time is difficult to determine. who can give me a better resolvation.

 

[dtn_me]

Initialize all the inputs to proper value

 

[nand_gates]

You need to follow following steps.
1. Make sure that no input is 'x'
2. Initialize all uninitialized flops (flops not having reset pin) to '0' or '1' using deposit command.
3. Initialize all memorires in the netlist. For this you either need to hack the gatelevel memory model to write a task which initializes the memory or deposit the memory locations.
4. Disable timings for first sync flop at clock domain crossings. This you can do by forcing '0' on NOTIFIER reg in the coresponding flop instance.

Note that memory initialization must happen just after you remove reset.

After doing this if you get X's then be sure that they are because of some
timing violations.

Hope this helps!

 

[richardhuang]

thanks!