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Gate-level Netlist TO RTL Netlist

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Willt

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rtl netlist

Hello guys ~

I would like to know:
Is there any tools that can transform gate-level verilog netlist TO RTL verilog netlist?

Your guidance is highly appreciated !!

Will
 

ljxpjpjljx

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gate level netlist

as I know, few tools supports this function! why you need this ?
 

Willt

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apr rtl

Actually, I can do it manually.
But I want to know if there is any automatic way to do so.

The reason for the transform is for the sake of process independent.
After transforming gate-level netlist to RTL netlist, the RTL netlist can then be transformed to any process by synthesis.

Could you please name the tools?

Will
 

Adam.Yakuvitz

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what is gtech netlist

Willt,
You don't need to convert it to full RTL to make it re-targettable for other process nodes. You just convert the netlist into a generic netlist. That is . . for eg.

TI_NAND3 inst (.a(net1), .b(net2), .c(net3), out_z(net4));

would get converted to something like
and (net1, net2, net_and);
and (net_and, net3, net4p);
not (net4p, net4);

The latter netlist could be re-targetted for any process.

Cadence RTL Compiler or SNPS Design Compiler can both do these transformations. Make sure your converted netlists and retargetted netlist are all verified with Conformal-LEC against the original golden netlist.

Cheers!
-- ay
 

aznsj

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gtech ddc

As far as I know , you can use NClaunch..
 

fpga_asic_designer

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rtl gate level

I don't know if there are any tools you can use to transfer the synthesized netlist directly to a generic verilog independent to the technology.

but i guess there are two ways to make it true:
1. other than the netlist, define a mapping file to map the gates instantiated in the netlist into gates of the other technology lib ---hell lot of work though...
2. if you synthesize, don't do compile (at least for synopsys)
dump out the GTECH db/ddc/verilog after the elaboration. We have an IP with GTECH netlist, and both synthesis and ncsim can take the netlist. I would assume GTECH netlist can be taken by most tools...
 

mayanknaugaien

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netlist to rtl conversion

i think WILL by using NCLAUNCH u can convert gate level netlist to RTL

mann
 

ygggliu

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gtech netlist

the synthesis tools(Design Compiler) can help you transform the gate netlist to any process.
 

vibhute_r_p

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verilog gate level netlist library

IF no tool is giving you the expected result ..you can write simple perl script to do this translation

Ram
 

zhide

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verilog netlist of and gate

write a perl script, haha...
 

payal_asarawala

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gate netlist to rtl

You can compare gate level netlist and RTL Verilog I dont think you can do conversion
Willt said:
Hello guys ~

I would like to know:
Is there any tools that can transform gate-level verilog netlist TO RTL verilog netlist?

Your guidance is highly appreciated !!

Will
 

sunilbudumuru

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rtl to netlist

Hi Willt,

Instead of transforming from Gate-level netlist to RTL and then targeting to another process...

Synopsys Design-Compiler has a powerful command "Translate" that transforms your Gate-level netlist (process1) to Gate-level netlist (Process2)

If you want the flow, pls let me know.

Sunil Budumuru
www.asic-dft.com
 

vibhute_r_p

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rtl and netlist

Hi sunil,
I agree that we can use DC to do one ASIC netlist to other technology ASIC netlist, But what if i have asic netlist and i want to port that to FPGA....


Such a method is needed for this application.

Hi zhide,

I had written such perl script as my masters thesis. However it was targeted for one perticular technology. So netlists with that technology had been successfully converted and tested again on FPGA. I had also done Formality checks for original netlist and converted netlist.


Regards,
Ramchandra
 

sunilbudumuru

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conformal lec gtech -georgia

Hi vinhute,

Yes we can do that aswell.

Design Compiler FPGA is able to transform from ASIC netlist also. If ASIC synthesis netlist is the source you need to add the ASIC library in the link library list .
 

vongy

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rtl vs gate-level

but where is your RTL netlist?
 

sunilbudumuru

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design compiler netlist library

Hay, it will directly gives you the netlist that targets to your required FPGA . Then whts the necessaryof RTL netlist?

Sunil Budumuru
www.asic-dft.com
 

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