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Gate length to prevent hot electron transistor shifts

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rubink

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I am trying to track down some recommendations about gate lengths to prevent shifts in nmos transistor parameters vs Vds for 0.25um & 0.35um.
In the past I have come across tables from the foundry but I can't find any such information at the moment.
From memory I think the effect is worst when Vds = max (Vcc) and Vgs = ~ 0.5*Vcc.

thanks,
R
 

steer

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This is very foundry specific data. For one foundry I worked with in the past, 1um gate length was considered safe in most conditions.
You are right in your assertion about most dangerous operating mode.
 

electronrancher

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it depends, switching devices like inverters can be minimum length at full vcc (say 3.3v). non-precision analog like current mirrors would be 2x digital minimum, and precision mos like diffamp input stage should be very long and wide for matching. i usually find that hci is most problematic for high voltage constant current sources. but good matching always pushes my transistors to several x the process minimum, to the point where hci is not an issue.

i don't know a condition where i would run a device at vgs=1/2vds open loop. usually current is regulated by some other device closed loop. what's your application, specifically?
 

rubink

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My application is also for current mirrors & sources. The Vgs will depend on
sizing, current etc. The Vds will usually be less than Vcc but it may get close occasionally. I noticed that in Johns & Martin's Analog IC design book they recommended using longer devices for the cascode device in a cascoded mirror to reduce the stress on this device.
Somewhere else I read that the barrier between the Si and SiO2 is 3.1eV
which could mean the effect goes away below 0.35um but this is just a guess.
 

rubink

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I tracked down some data for a 0.35um cmos process:
For Vds =< 2.5V minimum gate length is fine.
For Vds =< 3.6V nmos gate length should be 1um & pmos 1.7um (for worst case Vgs = 0.5 Vds)
Really I am after 0.25u information but this gives some idea.
 

ambreesh

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In baker 2nd vol. he talks of keeping the gate lengths as high as 10 times the minimum feature size for subm and deep-subm technologies.
But , this must be take care of all the effects including hotelectrons.
 

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