Gate Induced Drain Leakage (GIDL)

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ssti85

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Hello,

Can anyone please explain the phenomenon of GIDL?
I am basically looking for its behavior in sub-threshold region.

I found the reference in a book where it says - the effect occurs for high CDS values in combination with low VGS values.

It would be great if someone could explain this effect.


Thank you.
 

When you take the gate negative and the drain positive,
that's a higher field sum than the usual VGS=0 logic case
most people look at for leakage. It increases acceleration
of carriers and impact ionization current in the body.

This is what makes drain leakage current rise again, after
bottoming, as you take Vgs more negative (NMOS).
 

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