gate driver with buffer of inverters

[aborigini]

Hi all,

I am designing an output stage for the class d amplifier. I am using buffer of inverters. I am not sure of the sizing of the inverters. What is the ratio of the PMOS and NMOS should be?
I am using tapering factor of 3.

I also add a deadtime to the signal and it creates distortion and shoot through current. Anyone can help?

Thank you very much.

 

[shaikhsarfraz]

Hi,
If you are taking tapering ratio of 3 thats ok, anyway that depends on how much drive current you want at the output.

Regarding what should be the ratio of nmos and pmos transistors, they should be optimised as per your requirement like if you want equal rise and fall time, or you want smaller delay.