Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Gain reduction techniques

Status
Not open for further replies.

Lt_Garillios

Newbie level 5
Joined
Apr 21, 2011
Messages
10
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,283
Activity points
1,336
What techniques are there to (in a controlled fashion) reduce gain besides altering the length?
 

you could play around with bias currents. Any architecutre in particular are you referring to?
 

you can control the gm(aspect ratio and bias current) of your input pair, ro of our loads (length, bias current) to get the required gain.
also depending on whether your input pairs are biased in saturation or subthreshold, gm could be lower or higher.
 

it depends on the accuracy you want. Gm is more affordable than rout of the loads. The better thing to do when setting accurate gains is to use architecture which provide gains given by the ratio of homogeneous quantities, such as resistances or transconductances.
 

First, please reduce gain stage numbers for gain reduction.
 

Source degeneration is pretty consistent. A cascade of
low gain stages can perform better than a smaller number
of high gain stages when it comes to bandwidth and low-
overdrive prop delay.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top