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Gain of op amp in bandgap reference circuit

Fesch

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Hey there,

I am currently trying to understand the bandgap reference circuit shown in the figure below. I am specifically trying to understand how to determine the needed open-loop voltage gain of the op amp.
The MOSFETs are supposed to be biased in saturation region and strong inversion. Ideally, the op amp input voltage difference should be zero. But in reality there will always be an offset voltage, even though the op amp inputs might be chopped to reduce the offset, the mismatch between the PMOS in the current mirror is still existent.
Assume that the maximum offset voltage (or error) at the input of the op amp is \[ V_{os} \]. Which is equal to \( V_{os} = V_{in+} - V_{in-} \). So I can say \( A_v \cdot V_{os} = V_{DD} - V_{SG} \). To make sure that the gain is sufficiently high it has to be larger than the output voltage divided by the input voltage:

\[ A_v > \frac{V_{DD} - V_{SG}}{V_{os}} \]

Is this approach correct? Am I not mixing small-signal analysis values with large-signal analysis values? Or are all those values large-signal values because they define my bias point of the circuit?
Thus, as an example:

\[ V_{DD} = 2 V\\ V_{os} = 500 \mu V\\ V_{SG} = 600 mV\\ A_v > \frac{2V - 0.6 V}{500 \mu V} = 2800 \]


Thanks for your help!

Bandgap_Ref_Circuit_B_Ravazi.PNG
Bandgap reference circuit, figure taken from B. Ravazi - Design of Analog CMOS Integrated Circuits
 

sutapanaki

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What concerns the opamp only, finite gain results in finte voltage difference between the inputs. Tihis is in addition to any other offsets in the circuit, or said in other words, even if everything else was ideally matched, you'd still have that dV. When you make a budget for how much difference between the inputs of the opamp you want, part of it goes to the effect of the finite gain. That part of the difference in relation to Vbe of Q1 is dV/Vbe <1/T where T is the negative feedback loop gain.
 

dick_freebird

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As op amp Vio will have substantial scatter, I think
it suffices to have the gain error on that order or
slightly less.

If your PMOS rack gate voltage needs a 1V swing to
accommodate PVT corners and your op amp has
a 10mV Vio distribution, then A=100 (40dB) ought to
be "barely good enough" (i.e. gain-error deviation
will sit within the Vio spread). Of course better hurts
nothing.

Unless you plan to trim because you are designing
a precision reference, not a housekeeping bias
reference. Then everything matters.
 

    Fesch

    points: 2
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