gain of dynamic latch comparator

[rmadhukarthi]

i am not able to increase the gain of the pre-amplifier stage beyond 2V/V. is this gain sufficient for the design. gain is low because the load for M1 and M2 transisters are in trode region(according to the design). how can I design the dynamic latch.

 

[rmadhukarthi]

how the resolution of the this latch can be increased. whether resolution is depending upon size of latches alone.....please help.

 

[hung_wai_ming@hotmail.com]

Check out "CMOS design, simulation and layout" from R.J. Baker.
Lots of references there

 

[ali12345]

I think the m1 and m1 must be in saturate region.then comparator works correctly