Fundamentals of RTL verification

[amjad]

I am new to the ASIC world ?

Can you help me to understand abou the RTL Verification exactly ?

or else Please let me know where can I get these fundamentals ?

 

[amaccormack]

Re: RTL verification

I'd recommend books by Ben Cohen, Harry Foster, Janick Bergeron and Andreas Meyer on the subject of verification.

Also, sign up for the verificationguild.org forums run by Janick.

 

[bismillah]

Re: RTL verification

Writing Test Benches by Janick Bergureon, also Morgan Kaufman, asic and fpga verification guide

 

[au_sun]

Re: RTL verification

Hi amjad,

U start the ASIC design flow by writing RTL codes either in VHDL or VERILOG,
when u have the finished RTL code, it must be verified that whether the RTL code will function as per design funtional specification and also it has to verified that it funtions correctly when it is placed in actuall design environment,
so for that u setup a verification environment where ur RTL code is placed in that environment and set of test vectors are fired to it,
the output for this set of test vectors from RTL codes are captured and they are verified for its correctness,
this is called RTL verification,

 

[reggae]

Re: RTL verification

typically, you need a verification environment to do rtl verification. Besides the DUT, you need a stimulus module and checker module, in most cases, you will need a reference model(as a golden reference). All the above are called behavioral models, they're written either in verilog or VHDL or vera or systemc, etc. The simulus module applys stimulus to the DUT, the checkers receive the response from DUT and compared with the response from golden reference model to judge whether the response is right or wrong. Further more, you will need several scripts written in shell scripts or perl or python, etc, which controls the running/regression of your environment. Besides simulation, you'll need a tool to do coverage anylysis.

 

[jjww110]

RTL verification

psl can accelerate verification process

 

[brianhe]

RTL verification

One of my friends develop the verification env with python. He said there is python module as PLI for rtl verification. Cool, isn't it?
I dont like vera/system verilog, may be because it is under developing by synopsys.
Specman(e language) is much better, but it is too expensive

 

[Thomson]

Re: RTL verification

The typical flow goes as follows:
(1) first verifies your RTL modules using VErilog/VHDL coded environment
(2) second verifies your sub-system consisted of RTL moduels to conduct the integrating testing using Verilog/VHDL coded environment
(3) the final system-level/chip-level enviornment building using BFM( bus functional modle)

The current state-of-the-art verification flow may alter within some aspects considering the occurrence of SoC:
(1) first using high-level verification language or modleing language such as SystemVErilog/SystemC to verify that the system-level's interface can function correctly
(2) then you go into the implementation of the respective sub-system macros which you shall also use high-level HVL to faciliate the efforts and reusability of the verification modules
(3) if all the above functions well, then the RTL implementation shall be verified using the BFM or the ordianry methods to verify the separated RTL modules

 

[beckchm]

Re: RTL verification

you must write testbench to verify whether your code is correct .

The RTL verification is for the goal .

 

[rchennam]

Re: RTL verification

Could you please suggest good book for Verification

 

[spauls]

Re: RTL verification

(1) Writting testbenches - Functional verification of HDL models.
(2) SOC Verification and Validation techniques.
(3) Principles of verifiable RTL design.
(4) Principles of Functional Verification.

 

[mura_krish]

Re: RTL verification

hi.,
im murali an B.E student beginer in verilog need some study material in this field so if u can send some material to my e-id ., mura_krish@yahoo.com.au

 

[sree205]

RTL verification

just search the forum krish, u ll find tons of material. especially the books upload/download section.

 

[yaseen1]

Re: RTL verification

RTL Verification means it verify the functionality of entire RTL Design

 

[yesme@]

RTL verification

U should learn how to make an efficient testbench file. RTL verification means that you build a testbench to test all functions of your system.

 

[yaseen1]

Re: RTL verification

We need to undersytand the flow of how Test becnh enivironment is and then you have to follow RTL Verification