Functional Issues in GLS

[paulki]

Hi guys,
Attention GLS experts!!!
Could you please list out the functional BUGS you found in the GLS (with or without timing, I mean ZERO_DELAY or SDF sims). Anything would be appreciable here.

-Paul

 

[chipmonkey]

There have been functional bugs.. but nothing that could not have been caught in RTL. It just happened that they were caught late in the verification cycle
here is one:
The design contains a divide by 3 clock divider. the requirement is that clocks must be free running and synchronous. since the divider is free running, resets does not affect the initial state of the flops in the divider circuit, ie in simulation they will be x. So it was required to initialize these flops to some value, ie 0 or 1. When these flops initialized with some random 0 or 1, for a particular combination it was seen that the divider was not giving the desired output.

This could have been caught in RTL as well as the design was in structural coding.

 

[paulki]

Hi Chipmonkey,
Thanks for your reply.
But this was not a "FUNCTIONAL" issue, rather the flop initialisation simulation issue in GLS. These issues were very well taken care by the GLS setup time itself. One more addition to your problem is very difficult to exercise all the possible random values to the initialisation of flops. Say a StateMachine has 6 flops and all the possible initialisation values and simulating the same will take lots of time and which is not really practical.

-Paul

 

[chipmonkey]

Paul,

it cannot be said that it is just a simulation issue. say i have 6 flops in my divider circuit; on silicon there is no guarantee which flop will initialize as 0 or which will initialize as 1. so if it happens that the flops did initialize as the failing scenario, then you do not have the clock and the design fails.
But as I said, you dont need a GLS to catch this. could have been caught in RTL as well.

It is rare to have a "Functional Bug" in GLS if RTL verification has been done properly. else if your cells have any issue then you have a functional bug.

 

[paulki]

Some classic examples listing out the Functional BUGs during GLS.

1. A block's Vdd connected to the Gnd pin in the netlist: No out put from that module (netlist renaming was the root cause)
2. Glitch free MUX selection path re-formed while doing the ECO (Wrong false path created timing issue).
3. RTL and GATE model's of a Particular Denali memory model were given 16bit Data and 32bit Data access respectively which cause serious test failure. Fixed with the vendor.
4. So on........ appreciates your contributions.......