Fully differential Amp common mode gain

[mirror_pole]

Hello guys,

Considering a fully differential amp:

I have both a differential and common mode gain that are non inverting. If i close the amp in a negative feedback loop why does it result in positive feedback for what concerns the common mode? Common mode gain larger then 1 would make the amp unusable.

 

[danadakk]

Curious, can you show a schematic implementation of your issue ?

Yes, if CM gain > 1 and you have positive fdbk you will get control loop saturating.


Regards, Dana.

 

[sutapanaki]

If you have a two stage amplifier, then for common-mode the external amplifier feedback (the one that you want for the differential operation) places the amplifier in positive feedback for the common-mode signals. This is because for common-mode you have two inverting stages in a loop. This can cause problems if you use one single CMFB that looks at the output common-mode voltage and feeds back to the 1st stage to correct the common-mode voltage.
I'm speculating here. Best is to show the schematic and some simulation results.

 

[mirror_pole]

hey guys here is the topology https: https://www.semanticscholar.org/paper/A-fully-differential-class-AB-OTA-with-CMRR-by-Centurelli-Monsurrò/fefedc5e9204b0b80f8d1d6349db65b44964a868/figure/0

Its a one stage fully differential class ab OTA with very poor common mode behavior. It can get as high as 16 db without CMFB and other aux amps. Both gains, differential and common mode are non inverting. I dont understand exactly why closing the amp in negative feedback for differential mode results in positive feedback for common mode

 

[BradtheRad]

Your link has a schematic containing current sources. These generate whatever voltage is necessary to deliver a set current level regardless of impedance in the current path being high or low. I can't help thinking current sources create unexpected circuit behavior. For instance suppose the only input is common mode, then do the current sources generate abnormal voltage levels throwing off normal common mode response? Such that common mode gain appears abnormally high?
I could be wrong.

 

[mirror_pole]

Hey, high common gain is present because of the flipped voltage followers which are biased with the current sources.
For example If you apply a common mode signal Transistor M1a has no signal comonent (Ugs,1a(t)=0) because gate and source have the same signal with same polarity. Therefore the current through M3 is set by IB but because of the foltage follower circuit the drain of M3 is signal dependant. Therefore Vg,3 has to change to compensate this dependance and to make sure that the current stays at its quiscent component IB. But this means that the NMOS output transistor M7 delivers a small signal current to the output.
Same argumentation for the Pmos part results in a non existing common mode signal component. And this difference is the main reason for the high common mode gain here.

Edit: This is an intuitiv explanation because exact calculation shows that there is also a common mode signal component through the Pmos part but compared to the Nmos part its negligible.