Jan 11, 2014 #1 R rids1 Newbie level 4 Joined Dec 4, 2013 Messages 6 Helped 1 Reputation 2 Reaction score 0 Trophy points 1 Activity points 33 module full_sub(a,a1,c,d,b,e); input a,a1,c; output reg d,b,e; always@(a1 or a or c) begin e={a,b,c}; case(e) 000: begin d=0; b=0; end 001: begin d=1; b=1; end 010: begin d=1; b=1; end 011: begin d=0; b=0; end 100: begin d=1; b=0; end 101: begin d=0; b=0; end 110: begin d=0; b=0; end 111: begin d=1; b=1; end endcase end endmodule
module full_sub(a,a1,c,d,b,e); input a,a1,c; output reg d,b,e; always@(a1 or a or c) begin e={a,b,c}; case(e) 000: begin d=0; b=0; end 001: begin d=1; b=1; end 010: begin d=1; b=1; end 011: begin d=0; b=0; end 100: begin d=1; b=0; end 101: begin d=0; b=0; end 110: begin d=0; b=0; end 111: begin d=1; b=1; end endcase end endmodule
Jan 16, 2014 #2 zel Member level 5 Joined Apr 5, 2007 Messages 88 Helped 13 Reputation 26 Reaction score 12 Trophy points 1,288 Location Kuala Lumpur, Malaysia Activity points 1,714 a lot of latches.
Jan 16, 2014 #3 R rids1 Newbie level 4 Joined Dec 4, 2013 Messages 6 Helped 1 Reputation 2 Reaction score 0 Trophy points 1 Activity points 33 plz tell me hw i can correct it........
Mar 10, 2014 #4 N nikhilna007 Junior Member level 1 Joined Jan 8, 2013 Messages 16 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 1,365 is it e={a,b,c}; or e={a,a1,c}; also 'e' is declared as one bit, but e={a,b,c} is three bit so the tool will truncate the three bit into one bit. so case expression never matches..
is it e={a,b,c}; or e={a,a1,c}; also 'e' is declared as one bit, but e={a,b,c} is three bit so the tool will truncate the three bit into one bit. so case expression never matches..