Full Bridge SMPS transformer best NOT interleave wound?

[treez]

Hello,
Here is two identical Full Bridge SMPS simulations in the free LTspice one has leakage inductance in the transformer, the other has perfect coupling (no leakage inductance).
Notice how the one with leakage inductance has far less severe reverse recovery of the secondary diode. (attached are waveforms of secondary diode voltage (green) and current (red).
I believe that leakage inductance in a Full Bridge SMPS is in fact advantageous to an extent, and there is no need to do “interleave winding” to reduce Leakage inductance in a Full Bridge SMPS transformer. Do you agree?

Also attached is the full bridge schem and the ltspice simulations.

 

[Easy peasy]

you've posted this question before, and there have been several good answers, when leakage is low enough that it does not interfere with power transfer, then it becomes a problem of the o/p diodes, for SiC the residual leakage is not a problem as the diodes turn off at about the time the fwd current drops to zero.

For slow Si diodes, the leakage must be reduced to a fairly low level unless you want big snubbers to dissipate the I^2L in the snubbers every cycle. Of course VERY low leakage (and slow diodes) will mean the driving fets will see the reverse recovery current better and larger and hence more losses (if you turn them on fast).

There is a sweet spot at full power for Tx leakage, affected by how fast you turn the fets on, the quality of the o/p diodes at max operating temp, how much snubbing (thermal and space) you can have - on both the diodes AND the fets!

This sweet spot could theoretically be determined by sim, but we have always wound Tx's for minimum practical leakage and varied the other parameters to give the best result (pass EMC, with min snubbing and reasonably fast turn on of fets)

 

[treez]

how much snubbing (thermal and space) you can have - on both the diodes AND the fets!

I suppose having snubber on the FETs is really good for EMC, but basically, the FETs in a full bridge are never going to see an overvoltage ring due to their vds voltage being clamped to the input rail by the intrinsic diodes, so surely we can get away without having snubbers on the FETs?

 

[Easy peasy]

Again to clean up RFI due to the mosfets, you can either turn them off a bit more slowly, or, have snubbers...

 

[mrinalmani]

I do not completely agree that there is no need to interleave the transformer winding in a full bridge SMPS.
For example consider 300nH total leakage inductance referred to the LV side of a 1:33 ratio transformer operating at 100KHz.
The reactance is 180mOhms referred to the LV again.The is very high and will not allow even 75A current from a 12V source.

 

[treez]

no arguments, if youre running that much current, then yes, leakage needs minimising

 

[Easy peasy]

For example consider 300nH total leakage inductance referred to the LV side of a 1:33 ratio transformer operating at 100KHz.
The reactance is 180mOhms referred to the LV again.The is very high and will not allow even 75A current from a 12V source.

This argument has also been used to say that the power obtained from a push pull output (2 diode centre tap) cannot be greater than "x", when in reality the leakage limits only the time required to ramp up to the desired current.

300nH is very high for the sec leakage inductance, for say 12V 75A, our 250V to 66V, 20A Tx's (35kHz) have about 200nH leakage all referred to the sec side, so I would expect 200/(5.5 x 3.75) = 9.7 nH scaled for V 66/12 & I 75/20

So for a 12V o/p and 9.7nH on the sec (all referred to sec) it takes only (V/L=di/dt) 61nS to ramp up to 75A with a 12V drive.

Even allowing for 250nS current rise time the Lleak-sec could be up to 40nH without trouble, and more for a centre tap o/p.

Still the Tx must be pretty good for 12V 75A, 100kHz, as typical trace inductance is ~17nH/ inch for open traces, obviously reducing the loop area where the Tx sec feeds the rectifiers is paramount and often 0.5mm thick etched Cu parts with only card or tape separation are often used to provide a very compact, low L arrangement for just these reasons...

 

[mrinalmani]

Hi!
Leakage essentially limits power and not just the current slope. The voltage drop across leakage reactance drops the terminal voltage.
I am not sure what you are referring to when saying primary or secondary. Lets talk in terms of HV side and LV side.
All my transformers are wound with ratio near 1:35 (12V:420V).
The magnetizing inductance (Xm) of the LV side is 50uH, leakage of 9.7nH is not even 0.02% of Xm!!! Even the wires connecting the transformer will have an inductance more than this!
Sorry, I did not understand your calculations, please could you explain?

Your transformer is rated 66V to 250V. The ratio is barely 1:4
My transformer is rated 12V:420V. Ratio of 1:35. Higher ratio means higher leakage.

 

[Easy peasy]

Our LF transformers are 7 layer, PSPSPSP, the output winding is 65V, 600uH, 200nH Lleak, all referred to sec (LV) this is 0.033% leakage (0.0167% if just the LV leak counted).

It would not be hard to generate a 100nH LV Llk Tx which is all you would need for 75A out

Remember once the current has swung in the o/p winding to +/-75A, it sits there increasing slowly due to the o/p choke, or driving voltage, so simply calculating the XL of the leakage referred to the o/p is not the whole story, the vector of the XL drop is 90 degrees out of phase with the IR drop in the secondary, so they don't add scalarly, but vectorially,

So 6.7milli ohm on the sec for 75A gives 0.5Vac drop, 100nH @100kHz, gives XL=0.0628 ohm (4.7V at 75A) which is not so bad as all it requires is a slightly higher driving voltage on the HV side, in the case of a centre tapped 2 diode o/p very few extra volts would need to be found on the HV side...

 

[treez]

I think the Full Bridge SMPS with full bridge secondary rectifier is a special case, and actually having more transformer leakage inductance (within reason) actually reduces dissipation in the secondary snubbers and primary FETs. The following two identical full bridge SMPS simulations bear this out. –One has k=0.996 and one has k=0.986, and the one with higher leakage inductance suffers less secondary snubber and primary FET dissipation.
(LTspice simulations attached, also a pdf schematic)

 

[Easy peasy]

It's fair to say you are assuming your diode models are perfect, when in fact they are likely pretty far from it...

 

[treez]

Likely to be true, but the models are the same for both of the cases above.

 

[Easy peasy]

So, two sets of bad results are better than one? I'll bet they (the models) have a similar response to twice the Vrev applied - which would give misleading results when the F.B. Tx is set for just above Vout, and the FWD Tx is set for > 2x Vout...

- - - Updated - - -

every fwd converter you ever see (hard switched) has heaps of snubbing...!

 

[treez]

Thanks, so regarding post#10, you think a full bridge smps (with full bridge secondary rectifier) with more transformer leakage would always have more snubber loss than a full bridge smps with less transformer leakage inductance? (considering that they had the same RC snubbers)