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full adder vhdl program using for loop only

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balayoga

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can any one understand how i want to write program of full adder and give me solution
entity adder is
Port ( a : in STD_LOGIC_vector(2 downto 0);
b : in STD_LOGIC_vector(2 downto 0);
c : in STD_LOGIC_vector(2 downto 0);
so : out STD_LOGIC_vector(2 downto 0);
co : out STD_LOGIC_vector(2 downto 0));
end adder;

architecture Behavioral of adder is

begin
process(a,b,c)

begin

for k in "000" to "111" loop

so[k] <= [a[k] and b[k] and c[k]];
co[k] <= [(a[k] and b[k]) or (b[k] and c[k]) or (c[k] and a[k])];
--j<= i-1;
--k <= conv_binary(j);
end for;
end proces;


end Behavioral;
 

sanju_

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for k in "000" to "111" loop

so[k] <= [a[k] and b[k] and c[k]];
co[k] <= [(a[k] and b[k]) or (b[k] and c[k]) or (c[k] and a[k])];
--j<= i-1;
--k <= conv_binary(j);
end for;
this wont do full adder
what you want give more information....
so[k] <= [a[k] and b[k] and c[k]]; this wont do sum you have to use "XOR" in place of "and"
for k in "000" to "111" loop you can just use "for k in 0 to 7 loop"
 

Aritra17

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sum of full adder needs a xor gate not a and gate

and as far as i think your loop wont work that way
 

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