#### OKcomputer6

##### Newbie level 1

**full adder .. help**

i have just learned to write on vhdl and I have completed my first full adder code using components for the xor, and, or gates but im not sure if its right, could someone please tell me if this is right? I do not have vhdl ive written this on notepad..

-- For XOR gates:

library IEEE;

use IEEE.std_logic_1164.all;

Entity XOR_1 is

Port (x,y : in std_logic ;

z: out std_logic)

Architecture behavioural of XOR_1 is

Begin

Process (x, y)

Begin

If (x /= y) then

z <= ‘1’;

else

z <= ‘0’;

end if;

end process;

end XOR_1;

-- For OR gates:

library IEEE;

use IEEE.std_logic_1164.all;

Entity OR_1 is

Port (a1,b1 : in std_logic;

c1: out std_logic);

End OR_1

Architecture behavioural of OR_1 is

Begin

Process (a1, b1)

Begin

if ((a1 = ’0’) and (b1 = ‘0’)) then

c1 <= ‘0’ ;

else

c1 <= ‘1’ ;

end if;

end process;

end OR_1;

--For AND gates:

library IEEE;

use IEEE.std_logic_1164.all;

Entity AND_1 is

Port (i1,i2 : in std_logic;

out1 : out std_logic);

end AND_1;

Architecture behavioural of AND_1 is

begin

Process (i1, i2)

Begin

If ( (i1=’1’) and (i2=’1’) ) then

Out_1 <= ‘1’;

Else

Out_1 <= ‘0’;

End if;

End process;

End AND_1;

-- Full_adder:

library IEEE;

use IEEE.std_logic_1164.all;

entity full_adder is:

port (a,b,c : in std_logic;

c_out ut std_logic;

S1, temp1, temp2 ,temp3 ,ctemp : inout std_logic);

-- I used inout mode for ports used as an output in some statements and then as input in other statements.

end full_adder;

architecture structural of full_adder is:

component XOR_1 is

port ( x,y : in std_logic ;

z : out std_logic) ;

end component XOR_1;

component OR_1 is

port ( a,b : in std_logic ;

c : out std_logic);

end component OR_1;

component AND_1 is

port ( i1, i2 : in std_logic;

out1 : out std_logic);

end component AND_1;

begin

xor_ab : XOR_1 port map(x =>a, y =>b, z=S1) ;

xor_c : XOR_1 port map(x =>S1, y =>c, z=S) ;

and_ab : AND_1 port map (i1 => a, i2 =>b, out1 =>temp1) ;

and_ac : AND_1 port map (i1 => a, i2 =>c, out1 =>temp2) ;

and_bc : AND_1 port map (i1 => b, i2 =>c, out1 =>temp3) ;

or_ab : OR_1 port map (a1 => temp1, b1 => temp2, c1 => ctemp) ;

or_abc : OR_1 port map (a1 => temp3, b1 => ctemp, c1 => c_out) ;

end structural;

thank you!