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fsm states not displaying

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harerama

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HI ..i written code for 4 states fsm behav model and testbench model after ran in ghdl simulator only one state is displaying ...whats the problem?

entity mealy is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic_vector(3 downto 0)
);
end mealy;
architecture behav of mealy is
type state_type is (s0,s1,s2,s3);
signal current_s,next_s: state_type;
begin
process (clk,reset)
begin
if (reset='1') then
current_s <= s0;
elsif (rising_edge(clk)) then
current_s <= next_s;
end if;
end process;

process (current_s,input)
begin
case current_s is
when s0 =>
if(input ='0') then
output <= '0';
next_s <= s1;
else
output <= '1';
next_s <= s2;
end if;

when s1 =>
if(input ='0') then
output <= '0';
next_s <= s3;
else
output <= '0';
next_s <= s1;
end if;

when s2 =>
if(input ='0') then
output <= '1';
next_s <= s2;
else
output <= '0';
next_s <= s3;
end if;


when s3 =>
if(input ='0') then
output <= '1';
next_s <= s3;
else
output <= '1';
next_s <= s0;
end if;
end case;
end process;
end;

entity mealy_tb is
end mealy_tb;
architecture test of mealy_tb is
signal clk,reset,input:std_logic;
signal output: std_logic;
begin
uut: entity work.mealy port map(clk=>clk,reset=>reset,input=>input,output=>output);
process is
begin
input<='0';
wait for 2 ns;
input<='1';
wait for 2 ns;
input<='0';
wait for 2 ns;
input<='1';
wait for 2 ns;
input<='0';
wait for 2 ns;
input<='1';
wait for 2 ns;
input<='0';
wait for 2 ns;
input<='1';
wait for ns;
wait;
end process;
end;
thanks in advance
Regards
Raghavendra
 

sanju_

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Hi,
define clock in your test bench and try...
no clock is running so it wont see the rising_edge(clk)..
 

harerama

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Thanks ..i introduced clk in my program now also same problem..any other suggestions?
 

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