FSM more state vs less states

[shaiko]

An FSM can be designed with many states and little conditional logic inside each state.
An FSM can be designed with few states and a lot of conditional logic inside each state.

As far as I understand, the first approach will always yield better performance (speed wise) at the expense of more flip flops...Am I right?

 

[ads-ee]

It will also incur more latency to get the job done, so there is a trade off in terms of how performance is measured.

 

[K-J]

An FSM can be designed with many states and little conditional logic inside each state.
An FSM can be designed with few states and a lot of conditional logic inside each state.

As far as I understand, the first approach will always yield better performance (speed wise) at the expense of more flip flops...Am I right?

Two FSMs can also be designed with the exact same number of states and have a big difference in the amount of logic inside each state. A simple example of this is a decent size counter. When implemented as a straight binary counter, there will be more logic than when implemented with an LFSR counter. Same number of states, much different amount of logic.

Kevin Jennings