FSM: Moore or Mealy?

[HyperText]

Hi,

just a quick question... I have developed a FSM using VHDL and I'm questioning about if it is a Moore or a Mealy FSM.
Here is the code:

	-- FSM states
	type state is (idle, init, init_shift, subtract, test, operation_sub1, operation_sub0, correction, finished);
	signal current_state, next_state : state;

begin
	
	-- FSM
	control:	process(current_state, start, S_in, counted)
				begin
					-- Default signals
					en_M <= '0';
					en_Q <= '0';
					en_A <= '0';
					en_C <= '0';
					en_S <= '0';
					reset_reg <= '1';
					shift <= '0';
					stop <= '0';
					start_out <= '0';
					sub <= '0';
					
					next_state <= idle;

					-- Switch/case states
					case current_state is
						when idle =>
							reset_reg <= '0';

							if start='1' then
								next_state <= init;
							else
								next_state <= idle;
							end if;
						
						when init =>
							en_A <= '1';
							en_Q <= '1';
							en_M <= '1';
							start_out <= '1'
							next_state <= init_shift;
						
						when init_shift =>
							en_Q <= '1';
							en_A <= '1';
							en_S <= '1';
							shift <= '1';
							next_state <= subtract;
						
						when subtract =>
							en_A <= '1';
							en_M <= '1';
							en_S <= '1';
							sub <= '1';
							next_state <= test;
						
                                                -- HERE BEGINS MY DOUBT
						when test =>
							en_Q <= '1';
							shift <= '1';
							en_C <= '1';
							
							if counted=N/2-1 then
								if S_in='0' then
									sub <= '1';
									next_state <= finished;
								else
									next_state <= correction;
								end if;
							else
								-- Shift di A (e S)
								en_A <= '1';
								en_S <= '1';
								
								if S_in='0' then
									sub <= '1';
									next_state <= operation_sub1;
								else
									next_state <= operation_sub0;
								end if;
							end if;
                                                --

						when operation_sub1 =>
							-- Sottrazione SA=SA-M
							en_A <= '1';
							en_M <= '1';
							en_S <= '1';
							sub <= '1';
							next_state <= test;

						when operation_sub0 =>
							-- Addizione SA=SA+M
							en_A <= '1';
							en_M <= '1';
							en_S <= '1';
							next_state <= test;

                                              [...]

					end case;
				end process;
	
	-- Update FSM states
	update: 	process(clk_in, next_state, reset)
				begin
					if reset='0' then
						current_state <= idle;
					elsif rising_edge(clk_in) then
						current_state <= next_state;
					end if;
				end process;

For the first 4 states it is a Moore machine, right?
Then at the 5th state (where I wrote "HERE BEGINS MY DOUBT") I'm not sure anymore... "counted", "S_in" are input signals, while "sub", "en_A", "en_S" are output signals.
I don't know if it's useful or not, but the input signals are "clocked"/synchronized with the same clock (and phase) that I used in this FSM.


Thanks

 

[naught]

As long as the FSM takes external signals to decide its next state, then the FSM as a whole is s a mealy.
May I ask why you have those default signals be assigned to a certain value. Is it to prevent creating latch and avoid uncertain values?

 

[TrickyDicky]

As long as the FSM takes external signals to decide its next state, then the FSM as a whole is s a mealy.
May I ask why you have those default signals be assigned to a certain value. Is it to prevent creating latch and avoid uncertain values?

Default values are recommended for avoiding latches in a two process state machine template.

 

[HyperText]

Exactly!

Thanks for the answers...
I would add: could I consider that FSM as a Moore+Mealy (but described with one process)? Basically is Moore for certain outputs and Mealy for the other ones... Is this wrong?

 

[TrickyDicky]

I find it more helpful thinking "Does this state machine do what I need it to do" rather than sticking to specific mealy or more rules.

But yes you can mix the two styles in a single process state machine. You just make combinatorial outputs based on current state and any other signals.

 

[naught]

I find some of my friends code FSM in the following way:

---

Code VHDL - [expand]
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process(clk)
begin
  if(clk'event and clk = '1') then
    case(pr_state)
      when ** =>
        ****;
      when ** =>
        ****;
    end case;
  end if;
end process;

---

As far as I`m concerned...it`s a bad style, because when mixed in the "clk" condition, I have to consider the 1 clock delay.
Besides I`m more used to the textbook style, which is combinational part for output(it might get synchronized later) and the sequential part for the renewal of state.
But I`m not sure...

 

[TrickyDicky]

As far as I`m concerned...it`s a bad style, because when mixed in the "clk" condition, I have to consider the 1 clock delay.
Besides I`m more used to the textbook style, which is combinational part for output(it might get synchronized later) and the sequential part for the renewal of state.
But I`m not sure...

As far as many experienced engineers are concerned, its the best style, especially as a beginner, because it avoids all posibilities of latches. Yes all outputs are registered, but its easy to make a combinatorial output with variables or signals outside the process. The "textbook" style is around because in the old days synthesisors would only accept the 2 process method to extract the state machine, and some old designers still think in terms of combinatorial logic rather than data flow.

I do all my state machines like this. A 1 clock delay is not usually a bad thing (everything is pipelined anyway!)

 

[naught]

I guess it`s a career changing point... thanks a lot

 

[TrickyDicky]

The most important thing is easy to read, understand and well commented code. The style is not so important.

 

[FvM]

Referring to the original question, the FSM becomes Mealy type, if an output signals depends directly on an external input signal, not only internal states.

There are other important aspects of FSM design, that are not addressed by the Moore vs. Mealy alternative, e.g. the necessity to synchronize unrelated input signals to the system clock, or acceptance/avoidance of output glitches. The single/dual process topology is also not directly predetermined by Moore vs. Mealey.

My personal preference is single process FSM where both outputs and states are registered (set under clock edge control). As far it involves the possibility to have different output signals for the same state, it's a Mealey according to the scheme, if output signal combinations can be unequivocally assigned to states, it can be considered as Moore, although the actual functional difference is small.

To refer to the previous comment, the single process FSm is also straight forward and easy to read.