Frequency variation in PLL output frequency

[sakthivelmurugan]

Hi All,

I have designed PLL for 6GHz, which is perfectly locking. The question is, when i give "freq" function in cadence simulator calculator for the output frequency it gives the frequency curve over the transient time.(say 0 to 20us). when i see this curve, the frequency is 6G only but it has some +/- variation centered around 6G. The frequency variation is around +/-50Mhz. Is this acceptable?. please suggest me..

 

[THINKER_KAM_MAN]

Hi All,

I have designed PLL for 6GHz, which is perfectly locking. The question is, when i give "freq" function in cadence simulator calculator for the output frequency it gives the frequency curve over the transient time.(say 0 to 20us). when i see this curve, the frequency is 6G only but it has some +/- variation centered around 6G. The frequency variation is around +/-50Mhz. Is this acceptable?. please suggest me..

is that 5 parts in 600 ?
then better than 0.83% =8333 PPM not good.

as the reference frequency drift is multiply by the division.
you may need to use mixing down instead of dividing to
lock the phase loop it seems.
but it depends on your application if +-50Mhz is ok

 

[dick_freebird]

Are you taking your "freq" measurement using a window ("clip")
after you have achieved steady state? 20uS simulation time
suggests not, unless you have a very sporty loop filter (and
hence, perhaps less than stable).

If your freq for clip(v, 18u, 20u) and clip(v, 19u, 20u) are
giving you different results and the 18u window is worse,
then bet that you have not fully settled the loop and your
many-tau settling drift may still be skewing the loop some.

What is your lock-to-accuracy spec, the target accuracy
and the max tolerable time to get there?

 

[sakthivelmurugan]

Hi dick,
I supposed to check this after good settling only. The PLL settles at 5us itself. I checked at 20us which is same as the variation which we have in 10us. Even if i going to run this for 100us and check at 99 to 100us the same only am going to get

 

[sakthivelmurugan]

Hi thinker,
In my application, am going to use this 6Ghz clk for single edge sampling of 6Gbps data. i couldnt understand the first line 5parts in 600. will u explain me..

 

[D.A.(Tony)Stewart]

Where is your schematic? Divide ratio? Is it spectral noise jitter or drift?

5:600 = 50M:6G