Frequency multiplier using VHDL

[iVenky]

I know how to do frequency divider. But how to do frequency multiplier in VHDL?

The given frequency is the frequency of the clock.


Thanks in advance.

 

[emresel]

Hi;
As i know, in general DCM/PLL blocks inside FPGAs are used to multiply any clk.
But here is an example with another approach, using propagaton delay of logic cct. But i am not sure if it is successful in a real application.
VHDL coding tips and tricks: Combinatorial Frequency Multiplier Circuit in VHDL
Maybe some experts comment on it.
Good luck.

 

[rca]

As indicateur by emresel, you could générale rtl code bunt your must control the synthesis very carefully to preserve the delay cell to generate the phase clock before the XOR element.
One collegue did it with silicon success.

 

[DERNIB]

library ieee;
use ieee.std_logic_1164.all;

entity F2 is
port (fi : in std_logic; -- Input signal fi
f0 : out std_logic); -- fo = 2*fi
end F2;


architecture behav of F2 is
signal q,clk:std_logic;
begin

process(fi)
begin
if rising_edge(clk) then
q<= not q;
end if;
clk <= not (q xor fi);
f0 <= clk;
end process;

end behav;