Frequency locked loops

[mjxshipton]

Hey everyone

I've been scouring the internet looking for any information on frequency locked loops but it's been dismal at best. I'm not actually sure if a phased locked loop will do the same thing, but essentially I'm looking for something to automatically tune to a given frequency.

Is there a real difference between FLLs and PLLs? If so, where can I find information on this?

Additionally, I am trying to avoid use of modern chips like 4046s, instead preferring transistors, or even better, if possible, passive components only. I don't know if this is possible.

Could anyone help me shed some light on this?

I'm mostly interested regarding autotuning to a signal within a given bandwidth, such that the circuit would automatically retune itself to the strongest frequency.

 

[WimRFP]

You can make an FLL, but you will always get some frequency difference because of offset issues. In a PLL you may get a steady phase offset, but there will be zero frequency offset.

The "modern" phase comparators function as frequency comparators when out of phase lock and behave as phase comparators when phase synchronized. This saves you from sweeping the VCO to get it within the locking range.

You can make an FLL with a discriminator circuit (FM detector with DC output), If you need wide locking range, and can tolerate more frequency offset, you can use a one shot with an averaging circuit to get the DC value.

It can be done without hard digital circuits. By using a clipping circuit (such as used in FM IF chips), you can drive a voltage doubling rectifier via a small capacitor. Each transition results in a charge transfer that you can average over time to get an output that is proportional to frequency. You need to make some correction circuits to handle the temperature behavior of the RF rectifiers.

 

[mjxshipton]

You can make an FLL, but you will always get some frequency difference because of offset issues. In a PLL you may get a steady phase offset, but there will be zero frequency offset.

The "modern" phase comparators function as frequency comparators when out of phase lock and behave as phase comparators when phase synchronized. This saves you from sweeping the VCO to get it within the locking range.

You can make an FLL with a discriminator circuit (FM detector with DC output), If you need wide locking range, and can tolerate more frequency offset, you can use a one shot with an averaging circuit to get the DC value.

It can be done without hard digital circuits. By using a clipping circuit (such as used in FM IF chips), you can drive a voltage doubling rectifier via a small capacitor. Each transition results in a charge transfer that you can average over time to get an output that is proportional to frequency. You need to make some correction circuits to handle the temperature behavior of the RF rectifiers.

Absolutely epic reply, thank you, gives me a sound starting point.

 

[edick]

It may depend on your application, but I've been using all-digital PLL's implemented in programmable logic. The one I use relies on a very small deviation between the local master oscillator, which is used instead of a VCO, and the remote oscillator, the difference generally being the 100 ppm variation between crystal oscillators, from which the various data streams are timed. In order to retime the data to my local oscillator, I have to lock very quickly and my simple ADPLL does this within about one period of the data rate clock. That means it uses no more than 16 cycles of the master oscillator.

If you're working in the very high RF range, it's doubtful you can get logic to work that fast. Most loops that RF guys use will require 10-100x as long to lock, but will do the job, while my method works really well up to about 240 MHz for a master clock, so 1/16 that for a data rate. One other "issue" may be the phase jitter, which, is about 6%.