frequency drift in PLL design

[buyan]

pll bandwidth maintain divider

I have designed a PLL for 4000MHz output using a 20MHz REF from OCXO with synthesizer ADF4106. Loop filter is passive.

I use a divider to get three 20MHz REFs. One connects to Oscillator Scope, the second one is for PLL REF and the third one connects to a RS signal generator. I use a passive mixer to down converter the 4000MHz to 20MHz with LO from the RS signal generator. Then I connect the 20MHz output from the mixer to the Oscillator Scope too to compare with the REF 20MHz.

However, I found that the 20MHz output from the mixer is drifting during 12 hours continuously running watching period.

Please kindly advise what are the possible reasons? Thanks.

 

[FvM]

pll drift

Your setup hasn't get completely clear to me, if I understood right, you can consider three options: The REF OCXO is unstable, the PLL isn't locked or the signal generator has a drift. Which one do you prefer?

As you didn't tell a word about component specification and drift magnitude, we have to assume, that you are actually observing a drift beyond the expectable accuracy.

 

[buyan]

frequency drift

The setup is attached.

Thanks for your reply. I accept any reasonable explanation.

 

[wilwal]

phase locked loop design for single frequency

I cant open your set up PDF??

Key areas you should look at.

1.You oven controlled oscillator should be highly stable with extremely low phse noise as i will expect
2.What is the VCO you are using??Interms of the phase noise,Tuning sensitivity..... and the make...
3Are you using correct component values and type for your loop filter?You should understand that it is the loop filter that determines the dynamic of the PLL,i.e within the loop bandwidth.Beyond this the VCO takes over resuting in poor phase noise....

I suggest you look at you selected loop bandwidth and using Radio labs ADI sim PLL software for Analog sysnsthensizers you can simulate the whole PLL.
Play around with it till you get optimum values for your loop filter

You may consider using Active rather than passive filter in your design.Anyway Simulate with ADI simPLL and see what it suggests as the correct loop filter configuarations.

SimPLL is available for Free at Radio labs


All the best

Added after 9 minutes:


Hi Again;
Having been able to look at your set up,i suggest you undertake separate testing.

Before the you split your 20 MHZ signal,test your PLL using direct 20MHz from OCXO.If it works it might be the splitter that is affecting the RF level of the reference.
If not folow above design criteria as i mentioned above

Also i suggest you look at the values you programmed to you dividers N divider???

Is RF feedback signal divided correctly as you expect by the synthensizer?If not prerform necessary correction as this might be the problem

...........

 

[FvM]

pll locking problem at high temperatures

The drawing suggests, that the signal generator is synchronized (or what's the purpose of the reference input to the generator?). In this case you would see perfect synchronisized signals even with an unstable reference - if all signals are locked. But either this isn't the case or the setup is actually different.

 

[wilwal]

lmx2325 designed

??? LOck it to 20 MHZ

Instead of Oscilloscopes can you use frequency counter or spectrum anallyser.Mind you at the end you have to use spectrum analyser to measure both the phase noise of PLL and output of the mixer!!!

Check also you are using recommended resistors and capacitors at this frequency.

 

[FvM]

measuring frequency drift

??? LOck it to 20 MHZ

That's a question regarding the setup schematic, not a suggestion.

As mentioned before, nothing has been said about drift magnitude. So it's yet unclear, if the drift would be observable by a Spectrum analyzer.

As another comment: A PLL basically can't have a drift, to my opinion. It can loose lock, which can be easily determined at the phase detector. If it's locked, it can show jitter respectively phase noise, and of course suffer from a drifting reference.

 

[wilwal]

how to measure frequency drift

Yes VCO drit with frequency.A term normally called drift frequency of VCO?You will find it in any good vco datasheet.

Oven cook any PLL and you will notice that the output frequency drifts with temperature.
By the way you can observe a PLL locking condition on spectrum analyzer so to speak if you havent used one before.Set your locvk frequency to centre frequency and observe if it drifts left to right ===meaning not in lock!

 

[madengr]

choosing centre frequency of pll

It's probably the reference since there really isn't any way for the PLL and VCO circuitry to have a long term drift once it is phase locked.

I would not connect the signal generator to your reference unless you know the reference is much better than the generators reference. Check the manual.

One thing you can try is to compare your 20 MHz reference directly to the 10 MHz output from the generator. You can make a poor man's phase noise analyzer by storing the scope data over several hours then doing an FFT on your PC. I have observed sub-Hz stability problems like this.

A GPS-disciplined 10 MHz source can be had inexpensively now so I'd recommend getting one of those.

You also need to mention what is the magnitude of the drift and the rate of the drift. Is it drifting around a few Hz over a few seconds, or over much longer period?

 

[FvM]

phase lock loop active frequency drift

Yes VCO drit with frequency.A term normally called drift frequency of VCO?You will find it in any good vco datasheet

.
wilwal, I don't see your remark related to the previous discussion. Obviously a VCO has a drift. It comes in effect, when the PLL operation ends.

 

[BigBoss]

dect frequency drift

Signal generator and Oscilloscopes are not ideal mesaurment equipments. They also have drift behaviours due to internal references..
Frequency comparing of two signals is easily done double channel counters instead of scopes or SA..

 

[buyan]

how to determine frequency drift

Hi Wilwal,

Thanks. I have tried both passive and active loop filters simulated by ADISimPLL. I also checked the output signal from the PLL on spectrum analyzer. It's locked definitely. I saw you mentioned REF level and VCO specifications. Do you think REF level variation will cause phase drift? or any specification of the VCO will affect it?

Added after 8 minutes:

Hi Wilwal,

The phase drift is very obviously when putting the PLL module onto a hot plate. Basically, the temperature definitely affect the performance.

Added after 2 minutes:

Hi FvM,

Connecting REF to signal generator is to synchronize the PLL with the signal generator. Otherwise, you cannot see sychronized output on the oscillscope.

Added after 1 hours 6 minutes:

Hi Madengr,

"You also need to mention what is the magnitude of the drift and the rate of the drift. Is it drifting around a few Hz over a few seconds, or over much longer period?"

I attched one picture taken for the measurement. The arrow indicates the start point.
The system has been on for around one day.

 

[wilwal]

general drift frequencies

Yes;if your Reference frequency generator needs to be highly stable as this is the only input you have to be locked to!!!Think of a situation were both your REF is unstable;how will your feedbvack VCO signal lock!

After all we are using PLL to generate a stable and reliable frequency inorder to prevent errors in any communications systems.

Added after 1 hours 33 minutes:

Buyan,
You need to measure your PLL phase noise at specific offset frequencies using psectrum analyzer as recommended for your applications.e.g 10 HZ,10KHZ,100KHZ,1MHZ and compare with the recomendation as per dBc/HZ

If this is met your PLL works and you should look at other parts of your system as recommended earlier.

Refer to the following applications notes:
1.Phase-locked loops for high-frequency receivers and transmitters- Part 1 and 2by Mike Curtin and Paul O'Brien)
2.Maxim (APPLICATION NOTE 698)
3.How to debug a PLL frequency synthesizer by Bob kelly

Note carefully here;
Phase Noise in Oscillators:
•Because the LO signal is mixed with the received signal, any noise generated by the oscillator itself will add to the receiver noise.
•The predominant LO noise is referred to as phase noise because it appears as phase modulation of the LO signal.
.Any poorly desined VCO,the phase noise can seriously degrade the receiver performance

Remember!! That the higher the VCO gain, the more susceptible it becomes to external sources of noise and interference.

Finally follow the folowing design procedures for any PLL design:

Design Procedure for Phase Locked Loops:

1. Choose your VCO.
•If you are buying in a ready-made VCO, then obviously it must cover the range of frequencies that you expect, and with a given range of control voltage.
•The operating voltage and temperature range must be compatible with your requirements and, for battery-powered equipment, the supply current is also important.
• Check that the phase noise is acceptable (usually a figure is given for 10kHz offset, but more recently the figure may be given for integrated phase noise).
•If you are designing your own VCO, then follow the guidelines given below.
•


2. Choose your synthesizer chip.
•Practically all of the currently available synthesizer chips use a ‘charge-pump’ type phase detector.
•These offer several benefits over the older ‘voltage’ type phase detector, one of which is that it uses a passive loop filter instead of an active (op-amp based) filter.



Note:
•Unless your VCO is only required to operate at a single fixed frequency (as for a second LO in a dual conversion receiver), you will need a dual-modulus synthesizer with a built-in prescaler.
•Divider ratios available are typically 8/9, 32/33, 64/65 or 128/129.
•The choice will depend upon your VCO frequency (higher frequencies will need a larger division in the prescaler) and the maximum operating frequency of the main synthesizer block.
• The LMX2316 is an inexpensive low power type for use up to 1.2GHz and is an excellent choice for battery-powered equipment.
• For a higher performance, the LMX2325 might be considered.
• Other synthesizer manufacturers include Philips, Motorola and AMD.

3. Choose your ‘comparator’ frequency. (PFD input frequency)

•For multi-channel equipment, this will be pre-determined by the channel spacing - e.g. for GSM applications, the channel spacing is 200kHz and hence the comparator frequency should also be 200kHz.
•For PMR applications, the channel spacing is 12.5kHz and the comparator frequency will therefore also be 12.5kHz.
• Note that the comparator frequency must also be an exact sub-multiple of the VCO frequency - for example, 144.1MHz will divide by 0.0125, but 144.13MHz will not.
•For this reason, 144.13MHz would not be a viable channel frequency.


4. Choose your reference frequency

•The reference must be divisible by a whole number to give your comparator frequency.
•13 MHz will divide by 65 to give 200kHz or by 1,040 to give 12.5kHz, but 18.432MHz (a standard reference for DECT) cannot be divided to give 200kHz or 12.5kHz.
•In order to reduce the probability of in-band spurious products, it is a good idea to make the reference frequency as high as possible, although this will usually be limited by the maximum available divider ratio in the synthesizer chip.
•The reference oscillator is the main factor in determining the overall frequency stability of the system and also the phase noise performance inside the loop bandwidth.
• A simple crystal oscillator will have good phase noise, but relatively poor frequency stability with temperature variation.
•It is better to use a TCXO (Temperature Controlled crystal Oscillator) or VTCXO (Voltage and Temperature Controlled crystal oscillator).
•The latter type permits fine adjustment of the frequency by an external voltage and is occasionally used to allow direct frequency modulation (within the loop bandwidth).

5. Choose your loop bandwidth.

•As a general rule-of-thumb, the loop bandwidth should be a factor of ten times less than the phase comparator frequency.
•This allows adequate suppression of reference spurs, which would otherwise be present on the VCO output, giving the effect of greatly increased phase noise.
•Thus, for 200kHz channel spacing, the loop bandwidth should not exceed 20kHz, but for 12.5kHz channel spacing, the loop bandwidth must be only 1.25kHz.
•It follows that this also affects the loop settling time, which is a measure of how fast the loop can react to a change in frequency - the lower the loop bandwidth, the slower the settling time.
•Note: for this project, the loop bandwidth is chosen as the intersection point between the single side band phase noise of the VCO and the reference frequency
•Also we subtract 20 log 4 from the original values of the SSB phase noise due to the divide by 4 and it only applies to the Loop bandwidth frequency.

7.Determine the values for your Loop Filter.

•For most applications, a third-order loop is recommended - this means that in addition to the standard lead/lag-integrating network, there will be a further pole with a higher frequency break point.
•The purpose of this third pole is to attenuate the reference sidebands, which would otherwise appear on the VCO output to cause spurious responses in the adjacent channels.
• A typical loop filter is shown in the circuit at Figure below.





loop filter for a third-order loop.

•The lowpass filter effectively suppresses spurious signals produced by the phase detector so they do not cause unwanted frequency modulation in the VCO.
•The delay time of the filter, however, can result in degraded transient response and a limit in the switching speed of the frequency synthesizer.
•The transfer function of the third-order loop filter is given by;

Where Zfil2(s) describes the transfer function of the second-order loop filter given by:



Note but not sure: Interchange values of R2 and R3 for R1 and R2


•The main filter comprises C1, C2 and R1.
• R2, C3 provide an additional break point for the suppression of reference sidebands.
•The standard calculation invariably yields a high value for R2, but it is not always understood that R2 will directly add to the VCO noise figure.
•In practice, this value may be reduced within reason by scaling R2/C3, without significant effect on the main loop.

•Note that, for good noise performance, capacitors C1 and C2 should be high quality types.
•In order to calculate your loop filter, you will need the following information:
a). The charge-pump current. This is given in mA and will usually be in the range 1 - 10mA.
b). The VCO gain. This is given in MHz/V and will typically range from about 2MHz/V for a VCO in the 25 - 75MHz region to more than 50MHz/V for a VCO in the UHF bands. Because the VCO gain will not be constant across its control range, the mid-band value should be used. Some programs require this value in radians/sec, in which case the above figures should be multiplied by 2п x 106 Eg. 2MHz/V is equivalent to 12.56 x 10 6 rad/sec.
c). The total divider ratio, N (i.e. from VCO to comparator). Again, the mid-band value should be used.
d). The comparator frequency (in kHz). As already stated, this will usually be the same as the channel spacing.
e). Desired loop bandwidth (in kHz). In the absence of other directives, this should be one-tenth of the comparator frequency.
f). The desired Phase Margin. A good design should have a phase margin of not less than 40 degrees. Note that phase margin is also related to damping factor. For ‘critical damping’, d = 0.7, and this is equivalent to a phase margin of 37 degrees.
g). The minimum acceptable attenuation of the reference sidebands (specified by National as T1/T3 ratio). If sidebands are unimportant, this ratio can be 0% and the third pole (R2/C3) omitted. As was stated at the beginning of this section, it is not the purpose of this book to discuss ‘transfer functions’ and the complex math associated with calculation of loop filter values. Instead, it is expected that the practical engineer will use a computer program. I can recommend ‘EasyPLL’, which can be found on the Internet at:



Other Considerations:
•For good low-noise design, the power supply for the PLL must be stable and clean.
• It is therefore mandatory to use a separate, well-decoupled voltage regulator for the PLL section.
• For some very critical applications, the VCO will often have its own separate voltage regulator.
• Layout is also very important, especially in the area of the loop filter and VCO control line.
•The designer must ensure that the loop components are kept well away from any potential source of interference
•Digital switching signals can be especially problematic.
• Care must be taken with the routing of the reference (clock) signal, since any interference on this line will appear as spurs on the PLL output.
• Ideally, the entire PLL section should be self-contained in its own-screened compartment.



•Note: When the VCO is part of a phase locked loop, the phase detector (PFD) will effectively cancel the VCO noise within the loop bandwidth.
•Note: The dominant noise here is due to the synthesizer dividers and the reference frequency source.

•Outside the loop bandwidth, the VCO becomes the dominant noise source and the specification for a VCO will quote figures for SSB (single sideband) phase noise power at a specific offsets (1kHz, 10kHz and 100kHz) from the carrier or, alternatively, a figure may be given for the integrated phase noise (i.e. the integrated noise power over the output spectrum).

Added after 3 minutes:

Also note:

At lower frequencies rule for determing the loop bandwidth doesnt apply,rather you should look at the intersection of VCO Phase noise curve and reference curve where they cross is your loop bandwidth,
Hope all this helps

 

[madengr]

disciplined oscillator phase frequency detector

Hi Madengr,

"You also need to mention what is the magnitude of the drift and the rate of the drift. Is it drifting around a few Hz over a few seconds, or over much longer period?"

I attched one picture taken for the measurement. The arrow indicates the start point.
The system has been on for around one day.

If that's the phase drift over 1 day then I don't see what the problem is. It looks good to me. If your scope has deep memory you can sample over several hours then FFT to get sort of a phase noise plot. My guess is the phase noise is well below 1 Hz. A spectrum analyzer can't observe this, but this scope method can, or you can get a really expensive Aeroflex phase noise analyzer that can measure for hours.

Here is a video of a high quality source versus a cheap 20 MHz TCXO. The TXCO is +/-2 ppm. The video shows short term drifts up to 2 Hz which is still within spec of +/- 40 Hz. The manufacturer does not give phase noise data below 10 Hz. It's kind of obvious why. That +/- 2 ppm is supposed to be long term aging, but when it's just "frequency stability" it's open to interpretation.

**broken link removed**

 

[G4BCH]

how temperature affect pll

In your test set up you are relying on both the signal generator and the phase locked loop remaining phase stable over a prolonged time. This is not likely to happen, both will drift in phase with ambient temperature changes.
The PLL will do what ever it has to to maintain the stability output frequency, ithe phase relationship of the output signal with reference to the reference will change as the voltage on the variable capacitor changes. This is happening in both the PLL and the signal generator.
To see this effect in real time try loading the VCO output ( your finger will do ) and watch the output phase jump as the loop corrects for the change in VCO operating conditions.
Without making major changes to the test set up you have probably reached its measurement limit. You could try dividing the 3980 down to 20MHz, and use that as the REF1 & 2; a high speed divide by 199 may be a little tricky though.

 

[FvM]

drift in a pll systems

Referring to my initial comment, I see, that the assumption was apparently wrong. In so far I agree with madengr.

As you didn't tell a word about component specification and drift magnitude, we have to assume, that you are actually observing a drift beyond the expectable accuracy.

Connecting REF to signal generator is to synchronize the PLL with the signal generator.

The description isn't according to the setup schematic, I think. Still don't see exactly. what is synchronized here.