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They are designing an adpll, take a look at their other posts. Though I don't think it's a great idea to try and make a adpll in an FPGA (FPGAs are just too darn slow)
Am I missing something? Isn't this just a counter?
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They are designing an adpll, take a look at their other posts. Though I don't think it's a great idea to try and make a adpll in an FPGA (FPGAs are just too darn slow)
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