Can anybody give me the verilog code for fsm based frequency divider?
i need to use it for dpll
Why would anyone do that, when clock enables are far safer?
Am I missing something? Isn't this just a counter?
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They are designing an adpll, take a look at their other posts. Though I don't think it's a great idea to try and make a adpll in an FPGA (FPGAs are just too darn slow)