Frequency divider issue

[sprinter]

Hi,
I'm trying to simulate a frequency divider based on D Flip flop. I'm using a 0.12um process to divide a 8GHz source by 2. The divider is not working & I get a very weak voltage swing at 8GHz. The simulator (Golden Gate) gives a message that it recognizes a divide by 2 circuit but the self resonance is too weak. I tried changing the bias & sizing of the devices (all nfets) but it still doesn't work.

I shall highly appreciate feedbacks.

Thanks.

 

[saro_k_82]

With this information it is not possible to say much. Care to post your schematic?

 

[sprinter]

Thanks for your reply. Please have a look at the sch. & the waveformsm I'm sending as attachment.

I'm not drawing sufficient current (see the current at the VDD source). VB is the tail current but is not supplying enough although the mirrored transistor size is 10x the diode connected transistor which is at 160uA.

any comments?

 

[saro_k_82]

You must first check the dc bias points in your circuit. I see that the differential clock has a significant differential dc input. I dont see a reason for this.
In quiescent case, with both the clocks at zero level (plus some CMV), the tail current must be evenly distributed and the drop on the resistor should allow for a good differential swing.
The gain in the latch must be more than 2.

 

[sprinter]

Thanks for your reply. I fixed the problem. The clock had to be biased since for some strange reason the analogLib vsin instance's DC voltage wasn't working at all. Now I do get divide by 2 frequency.

The output swing depends upon the level of the tail current but it's less than that of the input clock. I'm not sure if I understood your point regarding a gain of 2 for the latch. Could you please elaborate that? - Thanks.

 

[saro_k_82]

If you have enough voltage room for the resistors to swing, but still dont see the swing, it is a bandwidth issue. You will then have to increase the current and reduce the resistance.
The latch has a positive feedback loop and the gain around this loop has to be atleast 2 in all cases at the operating frequency for it to latch the bit. Just do a loop gain analysis to find this.