frequency counter/meter in VHDL

[omerysmi]

I want to make a frequency counter in ALTERA DE1 with VHDL.
for the beginning I want to count frequencies between 1MHZ to 50Mhz(the main clock is 50mhz)
the result will show in 7 segment display.

I have tried to count rising edges of the main clock and according to this to calculate the measured frequency but it's not really good..

if you have a good idea for this i will be very happy to hear. i assume that is not very complicated..but i only need a direction.

 

[std_match]

The simplest approach is to use the fixed main clock to create a fixed measuring time. Since the DE1 board only has 4 digits you only need 10 kHz resolution.
If you count the unknown input signal cycles (= rising or falling edges) during 100 us you will directly get the frequency with 10 kHz resolution.

You can count the unknown signal in two ways:

1. Use it as a clock input to drive a counter. Since the 7-segment display on the DE1 isn't multiplexed, you can drive it directly from the input clock domain, but there are drawbacks. A more "serious" design is to drive the display from the base clock domain. This requires clock domain crossing logic to transfer the counted value to the base clock domain.

2. Synchronize the input signal to the base clock domain and do the counting with a state machine counter. This requires the base clock to be at least twicr the measured frequency. You can use a PLL to increase the base clock to 100 MHz or more.

 

[andre_luis]

I have tried to count rising edges of the main clock and according to this to calculate the measured frequency but it's not really good.

Which was the highest rate that you can achieve in the simulation ?

 

[omerysmi]

The simplest approach is to use the fixed main clock to create a fixed measuring time. Since the DE1 board only has 4 digits you only need 10 kHz resolution.
If you count the unknown input signal cycles (= rising or falling edges) during 100 us you will directly get the frequency with 10 kHz resolution.

You can count the unknown signal in two ways:

1. Use it as a clock input to drive a counter. Since the 7-segment display on the DE1 isn't multiplexed, you can drive it directly from the input clock domain, but there are drawbacks. A more "serious" design is to drive the display from the base clock domain. This requires clock domain crossing logic to transfer the counted value to the base clock domain.

2. Synchronize the input signal to the base clock domain and do the counting with a state machine counter. This requires the base clock to be at least twicr the measured frequency. You can use a PLL to increase the base clock to 100 MHz or more.

There is a way to make a simulation for 1Hz clock? because the vwf simulation time base is til 100us

 

[std_match]

There is a way to make a simulation for 1Hz clock? because the vwf simulation time base is til 100us

You can have any timebase in the simulation and in the waveform, but it is not smart to mix very different frequencies (like 1Hz and 50 MHz) in the same simulation. That will be a waste of simulation time. There should be no fixed "time base" for the simulation, you can use what you want.

 

[omerysmi]

You can have any timebase in the simulation and in the waveform, but it is not smart to mix very different frequencies (like 1Hz and 50 MHz) in the same simulation. That will be a waste of simulation time. There should be no fixed "time base" for the simulation, you can use what you want.

I want to change the end time to 1 second for example, there is no way to do it because the max end time is 100us so what can i do in this situation?

I do it beacuse i want to check how much clocks (of the measured clock) there are in a second, but I cannot check if it works when the end time of the time base is 100us..do you understand?

 

[TrickyDicky]

In modelsim just type

run 1 s

THat will run the simulation for 1 s

 

[omerysmi]

In modelsim just type

run 1 s

THat will run the simulation for 1 s

But i use in Quartus ii

 

[TrickyDicky]

If you're using the quartus 2 simualtor, then you are rather limited in what you can do.
I HIGHLY recommend you learn to use modelsim.

 

[std_match]

Regardless of the simulator, it is not a good idea to simulate 1 second if there is a 50 MHz clock in the design. You probably don't need more than 50 us simulation to fully test the frequency counter.

 

[omerysmi]

Regardless of the simulator, it is not a good idea to simulate 1 second if there is a 50 MHz clock in the design. You probably don't need more than 50 us simulation to fully test the frequency counter.

With my code i must use 1 second because i wait 50e6 rising edges until I get the final result..

look at my code to understand:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fcounter is
port(clk, m_clk, reset : in std_logic;
	  fout	            : out integer range 0 to 50E6);
end entity;

architecture arc of fcounter is
signal pulses : integer range 0 to 50e6:=0;
signal counter : integer range 0 to 50e6:=0;
signal flag : std_logic;
begin

	process(clk,reset)
		begin
		if reset='0' then
			pulses<=0;
		elsif rising_edge(clk) then
			if counter<50e6 then
				if m_clk='1' and flag='1' then
					pulses<=pulses+1;
					flag<='0';
				elsif m_clk='0' then
					flag<='1';
				end if;
				counter<=counter+1;
			else
					counter<=0;
					fout<=pulses;
					pulses<=0;
			end if;
		end if;
	end process;
end arc;

 

[std_match]

How long time does it take to simulate 100 us?
Multiply that by 10000 to get the simulation time for 1 second.

You should use as lower value for simulation and debugging, and then use the real value when implementing it in a real FPGA. You can use generics to automatically use a different value for simulation.

In your case there is no meaning to measure for 1 second since your frequency counter only has 4 digits. Count for 100 us. The count value can then directly be used on the display as MHz with two decimal places.

The frequency resolution is 1/(measuring time).

 

[omerysmi]

How long time does it take to simulate 100 us?
Multiply that by 10000 to get the simulation time for 1 second.

You should use as lower value for simulation and debugging, and then use the real value when implementing it in a real FPGA. You can use generics to automatically use a different value for simulation.

In your case there is no meaning to measure for 1 second since your frequency counter only has 4 digits. Count for 100 us. The count value can then directly be used on the display as MHz with two decimal places.

The frequency resolution is 1/(measuring time).

But if the end time of the simulation will not be 1 second i wouldn't see any result because fout (the output) get the final result only after 1 second..

 

[std_match]

Change the 50e6 constants to a smaller value to reduce the simulation time.

If you change to Modelsim you can simulate as long as you wish, but it is a waste of time to simulate a 50 MHz clock for 1 second when almost nothing happens.

 

[omerysmi]

Change the 50e6 constants to a smaller value to reduce the simulation time.

If you change to Modelsim you can simulate as long as you wish, but it is a waste of time to simulate a 50 MHz clock for 1 second when almost nothing happens.

I have tried to do it with Modelsim but it was rather complicated..there is no way to do it with Quartus?
I want only to check the final value of fout..

 

[omerysmi]

Change the 50e6 constants to a smaller value to reduce the simulation time.

If you change to Modelsim you can simulate as long as you wish, but it is a waste of time to simulate a 50 MHz clock for 1 second when almost nothing happens.

Ok I managed to do it in Modelsim and it works perfectly, thanks for the help!