Frequency counter-basys2

[boby251991]

I need to implement an auto-ranging frequency counter with VHDL for BASYS2

 

[mrflibble]

I need to do some groceries tomorrow. And to keep it electronics related, I need to debug this GNNNN ChibiOS thread that doesn't DoWhatIWant [tm].

Good luck on writing some specifications first! <== free hint of the day.

 

[boby251991]

I did

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity decodor is
port(
binar : in STD_LOGIC_VECTOR(3 downto 0);
iesire0 : out STD_LOGIC_VECTOR(6 downto 0)



);
end decodor;

--}} End of automatically maintained section

architecture decodor of decodor is
begin
with binar select
iesire0 <= "0111111" when "0000",
"0000110" when "0001",
"1011011" when "0010",
"1001111" when "0011",
"1100110" when "0100",
"1101101" when "0101",
"1111101" when "0110",
"0000111" when "0111",
"1111111" when "1000",
"1101111" when "1001",
"1110111" when "1010",
"1111100" when "1011",
"0111001" when "1100",
"1011110" when "1101",
"1111001" when "1110",
"1110001" when "1111",
"0000000" when others;

-- enter your statements here --

end decodor;




library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity divizor is

port(
sel: in std_logic;
clk_in1 : in STD_LOGIC;
clk_in2 : in STD_LOGIC;
clk_out1 : out STD_LOGIC
);

end divizor;

architecture divizor_a of divizor is
signal clk_out :STD_LOGIC;
signal semnalizare:std_logic;
begin

process(clk_in1)

variable cnt_int : integer;

begin

if clk_in1'event and clk_in1='1' then
if cnt_int < 50000000 then
cnt_int := cnt_int + 1;
clk_out <= '0';
else
cnt_int := 0;
clk_out <= '1';

end if;

end if;

end process;


process(clk_in2,clk_in1)

variable contor : integer;

begin
if clk_in2='1' then
contor:=0;
semnalizare<='0';
else
if clk_in1'event and clk_in1='1' then
contor:= contor + 1;
if contor =500000 then
semnalizare<='1';

else
semnalizare <= '0';


end if;
end if;
end if;

end process;


with sel select
clk_out1<= clk_out when '1',
semnalizare when others;





end divizor_a;



what files I need?

 

[aruipksni]

I need to implement an auto-ranging frequency counter with VHDL for BASYS2

the main problem here is that you are going to need to suply an acurate clock for the fpga.
if you use intrnal clock the measurement will be inacurate.

 

[mrflibble]

the main problem here is that you are going to need to suply an acurate clock for the fpga.

Not at all. A decent clock is trivial. A decent spec that someone can read to try and provide some help is less than trivial.

 

[aruipksni]

Not at all. A decent clock is trivial. A decent spec that someone can read to try and provide some help is less than trivial.

i don't think you are going to see any spec here ...

 

[mrflibble]

i don't think you are going to see any spec here ...

If the OP cannot be bothered to provide even a rough specification of what his freq counter should and should not do then too bad.

 

[boby251991]

How to do frequency divider?What remains to be apart from him and decodor ?

 

[mrflibble]

For the clue collection: https://www.google.com/search?q=fpga+based+frequency+counter

 

[aruipksni]

For the clue collection: http://www.google.com/search?q=fpga+based+frequency+counter

for the all enchilada :

**broken link removed**

see chapter 6.3

 

[mrflibble]

see chapter 6.3

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