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Free TSMC .35u compatible Engineering run

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Cathay

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tsmc .35u process information

Free Multi-Product Wafer Run on TSMC Compatible 0.35 um CMOS* Deadline for GDS submission is May 24, 2002 (*quantities limited - first come first served basis)

A consortium 8 inch wafer fab is offering a FREE 0.35 um TSMC compatible CMOS wafer run. This is an opportunity to test a new second source fab at no cost.

Please email sales for details, database requirements and to apply for space on the multi-product wafer run ("pizza mask")

Process information.

The following TSMC compatible process options can be fabricated on this
run:
- 0.35 µm Double Poly, Triple Metal Mixed Signal Process (Polycide).
- 0.35 µm Double Poly, Quadruple Metal Mixed Signal Process (Polycide).
- 0.35 µm Double Poly, Quadruple Metal, High Resistive Poly Process
(Polycide)

We will deliver sample dies or packaged samples in plastic or ceramic packages

Tape out deadline: gds data must be sent before May 24th

Fab out target date: end of August, 2002

Costs: all listed services are free of charge



I talk with the sales person and it is real. However, who can make
a TSMC compatible GDS database in a week? Please e-mail me
with your existing design and maybe we can make it before the
dead line

Who has Men+ :eek: or ADK (ASIC Design Kit) for HEP (Higher Education Program)
 

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