FREE 8051 IP Core from Oregano

[zotya]

oregano 8051

Hi there,

I've found the free 8051 IP core from Oregano, but unfortunately I have not found any sample project for this.
I'm a beginner in FPGA cores, so I need some help to implement this core in my project.

You can find this core here:
http://www.oregano.at/en/ip/index.htm

Thanks,
Zotya

 

[neocool]

free 8051 ip

Thanks, looks interesting.
I've played with 8051 cpu a couple of years ago. Maybe will take a look at it's hdl implementation soon.

What project are you planning to use it in?

 

[zotya]

free 8051 fpga core

Hi,

I need this 8051 core to control the communication to PC through a USB connection. It is a simple task for uC but not so easy for VHDL.
This communication is used for a DSO.

Regards,
Zotya

 

[ashishjindal76]

mcs51 cyclone

hi

ur implimentation smells g8 and i dont think that there shud be much difficulty with that.

ashish

 

[zotya]

8051 oregano

Dear Ashishjindal76,

Sorry but I do not understand your abbrevations, could you explain your answer more detailed?

Thanks,
Zotya

 

[iamchine]

nios 8051

Do you want to implement this core only in FPGA or with other modules such as USB modules?
This core is easy to understand.But it can't run at a high clock frequency.10 MHz at most in Xilinx Virtex FPGA.

 

[zotya]

usb ip core free

Dear Iamchine,

I will use FTDI USB chip out of SPARTAN, so I only need to handle the trafic to USB chip from internal logic.
It means that I'd like to use this core to control the system like a gateway.

As far as I know (from the autor) this core can run on higher speed in spartanII - than you mentioned. My only problem with this core the memories (RAM, ROM). I will have very small code in this case.

Regards,
Zotya

 

[iamchine]

Dear zotya,

Sorry,I can't get your meaning clearly.
Your problem is limitation of memories,right?
As I know,this core is same as standard 8051.It supports 256 bytes internal RAM,up to 64KB ROM and up to 64KB RAM.Do you mean you need much more code memory and data memory spaces?
How about your endpoint buffer?FIFO or dual port RAM?

 

[zotya]

Dear Iamchine,

First, thanks you help!

Let me shortly explain my problem.

I've tried to synthesize the 8051 IP core in Xilinx WebPack ISE 6.2.03i only for test (and learn) purpose. After some small modification almost all the source have been synthesized except the memories. I studied the core than I found that the memories should be connected externally to core (internal or external memories can be used). Here come my problems. How to provide the necessary memories? I know that SPARTAN II devices have internal RAMs, but I do not know how to provide ROM for the core internally in chip.
Unfortunately I have no experience in FPGAs and cores.

Have you ever check (or test) this core?

Regards,
Zotya

 

[iamchine]

Dear Zotya,
OK,I got it.
It's easy to solve your problem.How do you generate internal RAM modules? With Xilinx's Core Generator,right ? ROM is almost same.The
difference is Load Init File, .coe file(derived from binary code or hex code).Good luck!
Regards,

 

[iamchine]

Another way:you can add ROM bus to top module/entity's port and place a flash/EEPROM on PCB.

 

[keks]

hi everyone,

i have nearly the same problem as zotya. I have difficulties with the rams and "rom". I want to use the Block rams of the spartan2 FPGA, in order not to waste LUTs. To keep the thing easy i thought i could use one Block ram each->one block ram for internal ram(i know i am wasting memory), one for xram and one for rom.

After trying different things i could synthesize the whole design, but i doesnt´t work. Unfortunately i have no clue why. I initialize the rom with a very simple program which just sets a pin high or low. But the pin is always set as defined in the default values of the Port-SFR. This signals me, that the program does not run.

I would like to know if anyone has successfully synthesized the oregano core on a spartan2(or similar) FPGA. If so i would be very grateful for some help(architecture of rom,ram - Initialisation of the rom)

p.s.: I use the webpack free version->so i cannot use core generator(and to be honest i dont exactly know what it is for).

i hope someone can help

Regards,
keks

 

[dragon_boat]

hi everyone:
Are there someone who use altera device to do this?

 

[cluck]

look at http://www.oregano.at/en/ip/ip12.ht... 8051 Boot Loader Demo Design (Zip file, 3Mb)

 

[karsten2005]

hi all,

i also have a spartan2(development board by trenz). I tried to implement the oregano core to it in a similar way as keks but was not successful. I could synthesize and download it to the fpga but the testprograms showed only that it doesn´t work.

I have tried some other cores as well.

The only one i could successfully use is the one from **broken link removed**.

It´s easy coz the design is implemented with a spatrtan2 using blockrams. To compile one can use sdcc(forget not to use the option that tells the compiler to use 128 byte ram->it doesnt work otherwise).

The only problem about that 8051 model is that interrupt controller and timers are missing, so u have to poll.

hope it helps.

 

[karsten2005]

hi again,

good news : the oregano is running on the spartan.

this is the simple code i use to realize the ram(the rom and xram can be realized the same way):

architecture struct of mc8051_ram is
component RAMB4_S8
port(DI : in STD_LOGIC_VECTOR (7 downto 0);
EN : in STD_logic;
WE : in STD_logic;
RST : in STD_logic;
CLK : in STD_logic;
ADDR : in STD_LOGIC_VECTOR (8 downto 0);
DO : out STD_LOGIC_VECTOR (7 downto 0));
end component;
begin
U_ram : RAMB4_S8
port map(DI=>ram_data_i,EN=>ram_en_i,WE=>ram_wr_i,RST=>reset,CLK=>clk,
ADDR(6 downto 0)=>ram_adr_i(6 downto 0),
ADDR(8 downto 7)=>"00",
DO=>ram_data_o
);
end struct;

And make sure not to use too high clocks. I started with 48MHz what caused strange effects(although most of the prog worked).I use 6 MHz right now, but 12 should work as well.


regards

 

[bakabaka]

I have used the model provided by karsten2005 to define the ram, ramx. I can synthesize the design.. but still doesn't work. From what i've been reading i need to have some timing constraints but i don't how to do that.. also i'm having some problems with loading the rom with compatible hex code. Anyone managed to this?