Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Frame buffer and clock speed question for Virtex 5 board

Status
Not open for further replies.

vjabagch

Member level 1
Joined
Jun 26, 2009
Messages
35
Helped
4
Reputation
8
Reaction score
4
Trophy points
1,288
Activity points
1,665
I have been trying to get a diagonal line to show up on my screen using a Virtex 5 (V5LX110T) board. It has an external ZBT SRAM chip which I am using as a Frame Buffer.

So far, I have written a series of sequentially incrementing data values at sequential memory locations and have been able to read them back using chipscope. I can verify that the values read back are incrementing.

When I connect my SRAM module controller to a Dual Port RAM I can not successfully write (non zero) data values to the DPRAM. I have checked chipscope and the write enable is always high which is supposed to be high when I read back a non zero value from SRAM. Consequently I see a scrolling pixel on one line of my screen.

I am running my SRAM at 100MHz and writing to the DPRAM at 100MHz. My read clock on my dual port ram is 25 MHz (pixel clock frequency).

Is 100 MHz too fast for the FPGA? Even at a slower 12.5 MHz (1/8 of the speed) I see the scrolling pixel on my monitor and not a static diagonal line.

Also I was wondering if the Block Rams could be used in place of the SRAM for buffering the video frame?

Thank you for the help.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top