fractional_N PLL realization

[cirand]

meninger perrot

Does anyone has the experience on fractional N PLL design?
it seems very difficult to implement it in a chip for me. many papers
have describled the FN-PLL principle, but few of them refer to the detailed realization methods.Can anybody give me any advice ? such as what is the design flow, which tool should be to use, and any good articles on this field? thanks.

 

[amitbhaiji]

meninger pll

Hi,
There are lot of method to implement FN-synt i am mentioning two of them.

1) using the MASH-type of sigma delta modulaor in the frequency divider path. Which will remove the periodic noise (dither) in the feedback path and hence reducing the fractional spur in the synt output. Effectivly by using the sigma delta modulator we are forcing the quantization noise out of band of interest and which is then removed using the loop filter.
* Matlab modlling will be the most viable option for the same.
* Regarding some reference ther is one good thesis by michel henderson perrot (i think so) freely available on net.

2) Other method will be to use phase interpolator at the output of the VCO and then by toggeling between various phase one can obtained fractional division.

we can disscuss more..

Amit

 

[cirand]

sigma delta pll ieee

the second method you refered is easy to follow, but as i know this
method has not good phase noise performance. the sigma delta fnpll
by far has the best performance, is this true?
In frequency domain ,the principle of the sigma-delta FNPLL is clear and
easy to grasp, but the terms in the paper refered are so abstract,( especially in 2nd order or higher order) i can't understand what they are in the time domain,for example , in frequency domain, the DSM is used to
push the quantizer noise to high frequency band, but what is the quantizer noise ? in high order DSM , there are many quantizer noise Q1,Q2,Q3... are they same? if not , what are they represent respectively?

amitbhaiji, can you give me the URL of michel henderson perrot's thesis?

our Chinese new year is coming , I wish all people can share our jollification at the same time!

 

[amitbhaiji]

frac-n pll thesis

yes second method is easy to follow but tough to design as design of the tap selection and interpolator will be very tough..
while first method is tough to follow but eay to design..choice is yours..
well regarding quntization noise it is the diffrence between the division ratio of the divider and the actual division ratio we want to obtained from
divider.
As you might be aware we obtaine the fractional ratio by selecting between the various integral division ratio..and the diffrence between this
two ratio is what we call quantization noise..
So now question come how sigma delta usefull..
1) we are doing the oversamling so distribuing this quatization noise over wide band.
2) Sigma delta act like high pass filter to the quatizaton noise and hence furthere reduce in band noise.
3) Sigma delta modulator dithere the quantization noise and hence to first order remove any perodicity and hence remove fractional spur.
hope that you are able to follow..
more you can get on google by searching for white papere on frational n synt from connexant now called as skyworks..
here i am forwarding you good link of phd and some model for fraction n
http://users.cybercity.dk/~bse1977/phd/

hope you will enjoy going through it.

Amit

 

[cirand]

users.cybercity.dk/~bse1977/phd

thank you very much ,i agree with your views on the two different method to implement the FNPLL.
I have read Thomas Stichelbout's thesis,and i do know the quantization noise is the error between the instantaneous divide ratio and the ideal divide ratio. but i still don't understand why so many different quantization noise are refered , ( sorry for my stupid question, i am a beginner :wink: )
and another question : what is oversmapling meaning in FNPLL? in ADC
the oversampling means the sample frequency is times higher than the 2*Nyquist frequency , so quantization noise is spreaded over a wide band, while in FNPLL , the sample frequency is the fixed at the input frequency, how to oversample ? :?:

 

[ccw27]

perrot fractional

Does anyone have the thesis located in http://users.cybercity.dk/~bse1977/phd/
Please post it, the link seems to be broken.

Thanks

 

[vijay_nag]

mtt_2004_meninger.pdf

hi!

there is one technical document by texas instruments on Fractional PLLs. i am posting the link- **broken link removed**

regards,
vijay

 

[eng_Semi]

mtt_2004_meninger.pdf

Is there any books describe the fractional-N PLL? or all the resources are some papers?

I also need a resource which describe the fractional-N PLL, even if it was one chapter like the one in Razavi which discuss the integer-N type.

Thanks in advance

 

[Japp]

users.cybercity.dk/~bse1977/phd

Is there any books describe the fractional-N PLL? or all the resources are some papers?

Yes there are books e.g CMOS FRACTIONAL-N SYNTHESIZERS by Bram de Muer and M. Steyaert. This is pretty much the Phd thesis from DeMuer.

Personnally I was not that crazy about Stichelbout's thesis. I much preferred Perrotts (https://www-mtl.mit.edu/~perrott/).
But you can actually find a lot of good papers about the subject (and thesis) which shows just as much as the books.

Another resource is the US Patent office (https://www.uspto.gov/patft/index.html) Many patents have detailed descriptions of the architecture (Yes, it patented...) for example showing the correct number of flipflops at the output of the accumulators carry output (these details are often omitted in the papers, maybe to confuse those trying to make one themself..).

Added after 1 hours 10 minutes:

Does anyone have the thesis located in h**p://users.cybercity.dk/~bse1977/phd/
Please post it, the link seems to be broken.

Thanks

Hi, I have uploaded it here

(I am not sure if it is permitted to upload files in this forum..)

 

[mr_chip]

pll thesis

what is oversmapling meaning in FNPLL? in ADC
the oversampling means the sample frequency is times higher than the 2*Nyquist frequency , so quantization noise is spreaded over a wide band, while in FNPLL , the sample frequency is the fixed at the input frequency, how to oversample ? :?:

Here oversampling is:

OSR = Fref/(2*Fc),
where Fref is the reference frequency and Fc is the cross-over frequecny of the PLL.

Added after 3 minutes:

Hi folks!

I wanted to have a look at Perrott's thesis, but for some reason his MIT's page is unaccessable for me. Can someone please upload the thesis here or PM it to me?

 

[ccw27]

perrot pll

Does anyone have this thesis?

J. Craninckx and M. S. J. Steyaert, "Low-phase-noise fully integrated CMOS frequency synthesizers," Phd dissertation, Katholieke Univ. Leuven, Belgium 1997

 

[Puppet1]

pll phd thesis

Read This:

S.E. Meninger, M.H. Perrott, "Sigma-Delta Fractional-N Frequency Synthesis," 2004 IEEE MTTS, Fort-Worth, TX. PDF

https://www-mtl.mit.edu/researchgroups/perrottgroup/Publications/Talks/MTT_2004_meninger.pdf

 

[thstich]

fractional pll dsm noise

Perrot's thesis is sure a great reference. There was not so much documentation available on that theme at the time.

I have attached a copy of my thesis ... you can always use the litterature list.

.. i don't have that much space on my webpage at cybercity & they deleted the copy available at aalborg university website a couple of years after i left the university.

T stichelbout.

 

[ls000rhb]

to :thstich
how to open *.ps file?

 

[davidwong]

Any sigma delta modulator example in circuit level.
I read the paper IEEE Transaction on Instrumentation and Measurement VOL 40, No3, JUNE 1991.
a three stage sigma delta moduletor is implementated by accumulator.
I can read the similar structure in some other paper or thesis.
but I do not have any idea on implementing 1/z.
how can I implement the 1/z?
simply a invertor delay?

thx

 

[mists]

On windows operation system, gsview is a good choice for .ps file view.