Fractional Synthesizer question

[liberal]

Hi:
I want to design a synthesizer at 800MHz-1300MHz with 125KHz steps,I want to use ADF4153 a fractional synthesizer ,is it ok?and how to choose the loop bandwidth?I choose 50Khz,is it ok?what about designing with DDS?Thank you!

 

[ebalboni]

Yes the FRacN PLL is a good option. The PLL bandwidth should be set to smaller than 50kHz if at all possible to reduce spurs at the output. ADI has a free downloadable program to simulate operation with thier PLL. See: http://forms.analog.com/form_pages/rfcomms/adisimpll.asp