fractional N frequency synthesizer for low IF RX targeting lte

[ali kotb]

hello
I am targeting the FDD lte band uplink(1710-1770)MHz , downlink(2110-2170)MHz

from the 3gpp standard :

A. I figured out that there are more that 1 channel BW (1.4 , 3, 5, 10, 15, 20 MHz)
what are the criteria for choosing the BW value for smart phones Rx design ?

B. about the frequency plan of the Rx , what is the most used IF frequency for lte generations (low IF Rx) ?
I have gone through "Qizheng Gu, RF system design of transceivers for wireless communications" but it has no info about lte

C. from the blocker profile , I found that their are no blockers before 7.5 M offset
so what will judge the close in phase noise for the synthesizers ?

D. how to calculate the PLL locking time for the lte standard ?

E. how to calculate the SNR needed for estimating the phase noise of the synthesizers (i know it needs alot of details about BER and communication concepts , but i am interested in the Rf design only , so can any one give me a reasonable value for the SNR target ?)

 

[AP31]

hello
I am targeting the FDD lte band uplink(1710-1770)MHz , downlink(2110-2170)MHz

from the 3gpp standard :

A. I figured out that there are more that 1 channel BW (1.4 , 3, 5, 10, 15, 20 MHz)
what are the criteria for choosing the BW value for smart phones Rx design ?

B. about the frequency plan of the Rx , what is the most used IF frequency for lte generations (low IF Rx) ?
I have gone through "Qizheng Gu, RF system design of transceivers for wireless communications" but it has no info about lte

C. from the blocker profile , I found that their are no blockers before 7.5 M offset
so what will judge the close in phase noise for the synthesizers ?

D. how to calculate the PLL locking time for the lte standard ?

E. how to calculate the SNR needed for estimating the phase noise of the synthesizers (i know it needs alot of details about BER and communication concepts , but i am interested in the Rf design only , so can any one give me a reasonable value for the SNR target ?)

In general, I need more detail of what you're trying to design. Yes - you're designing a synthesizer, but what is it driving? Regarding "E" it totally depends on what levels you're trying to detect (minimum detectable signal, which is calculated by the following formula (MDS (dBm) = [-174+3dB] +10*log(Bw(hz))+Noise Figure (dB).

Close in phase noise (<10KHz) is dominated by the reference clock & flicker noise, while far out phase noise (>10KHz) is dominated by noise floor of the PLL IC. So the cleaner the reference oscillator, the better the overall close in phase noise of the synthesizer will be. To calculate the PLL noise floor you'll need the floowing parameters; PLL FOM (figure of merit), PFD (the phase detector frequency) and "N" (where N is the divider value). PNsynth = FOM (dBc/Hz) - 10log(PFD) - 20log(N).

But before you apply the above calculations, you'll need to determine what you're system parameters need to be before decomposing requirements. For example before you calculate the synthesizer performance you want to calculate the overall receiver noise floor so the synthesizer doesn't desensitize the radio. Some useful formulas below;

Signal/Noise[dB] = 174+ RX_Sensitivity[dBm] – 10*LOG(BW[Hz]) – Noise_Figure[dB]
Noise_Floor[dBm] = – 174 + 10*LOG (BW[Hz]) + Noise_Figure[dB] + Gain[dB]
Minimum_Detectable_Signal[dBm] = [–174 + 3dB] + 10*LOG(BW[Hz]) + Noise_Figure[dB]
RX_Dynamic_Range[dB] = RX_Sensitivity[dBm] – P1dB[dBm]

Regarding lock time, there are several factors that go into this, but it's heavily dominated by the loop bandwidth. Based on the PLL you're using, you can simulate the lock time using various PLL sim tools. Again, you need to define system parameters before decomposing requirements.

Hope this helps a bit.

 

[ali kotb]

thanks
that needs a complete system design on ADS for the RX .
since I am only concerned about the Synthesizer, can u give me the blocker profile for the lte (for any value of the above mentioned specs SNR, channel BW, sensitivity , etc)

Regards, Ali

 

[RFDave]

The Blocker specs are all in the LTE radio level specifications, and it looks like the tables in your post have most of the details for the blocker spec.
Low IF architectures have real problems with image performance, as your image frequencies tend to be a couple of channels away. It appears that all of the commercial chipsets have moved to direct conversion architectures, so that's probably a good starting point.

As far as how to determine lock time for the synthesizer, you need to look in the spec for channel switching time requirements, and that will drive your Synthesizer lock time requirements. Once you have that, you can figure out the loop filter bandwidth you need, and then start looking at phase noise requirements.

Or, you could go digging in the IEEE JSSC papers from 2011 and 2012 for papers on cellular synthesizer design, and use their design requirements.

 

[ali kotb]

thank u
one more Question : for lte Rx which use OFDM for the downlink, I didn't find in the above tables any blocker requirement <7.5 MHz offset for 10 MHz channel Bw. which is weird for me , there is no blockers closer to the signal frequency ?
what about sub carriers and their role for defining the phase noise specs for the synthesizes ?

 

[RFDave]

You'll need to look at adjacent and alternate channel rejection specifications to get closer in than 7.5 MHz.

Sub carriers for OFDM impact phase noise specifications differently, depending on their spacing. I don't remember enough to tell you what the behavior is, it's been 4 or 5 years since I looked at that.

 

[ali kotb]

what defines my channel BW (1.4M , 3M, 5M, 10M, 20M ) ?
should the Rx target a certain channel BW or all of them ?
and if the Rx can receive all these channel Bw , what is the purpose of the adjacent and alternate channel rejection specifications ?

Regards

 

[RFDave]

Your channel bandwidth is set by the system configuration. A real product would support all of them.

There would be switchable channel filters for each rx bandwidth, to meet the adjacent/alternate channel rejection. You need to figure out this, and then derive the appropriate phase noise profile that will meet the requirements of all of the channel bandwidths.