Fractional interpolation/decimation filter implementation

[tigger]

decimation filter

How do I implement a fractional interpolation/decimation filter in hardware? I know how to do an integer interpolation/decimation filter (by using polyphase filters), but don't know how to do a fractional one without overspeed. For example, to convert 100MHz sampled data to 90MHz, the decimation factor is 10/9. Mathematically it can be done by 9x interpolation followed by 10x decimation, but that means 9x overspeed, or 900MHz clock for the polyphase filters. Can this be done using only 100MHz clock?

Thanks.

 

[ramesh]

fractional interpolation

You may have to use RF PLL to obtain 900MHz from 100MHz. But I don't know how to realize hardware for digital interpolation and decimation for such a high frequency.

 

[brmadhukar]

sync decimation filter

Such frequencies are nearly impossible currently. You will have to sample at lower rate and frequency

 

[dll_embed]

decimation interpolation

For this kind of high frequency, you can't directly use the simple direct way as you mentioned.

I assume your data is bandwidth limited. Then after low pass filter you can use a NCO to directly sample the 100M data at 90M. The issue here is to get an accurate 90M, you need an higher source to clock your NCO.

regards

 

[ramesh]

fractional decimation

Without going to analog domain (i.e. without using analog low pass filter to band limit) is it possible to direclty sample using NCO at 90M? I mean is it possible by digital means only?

 

[dll_embed]

fractional decimation realization

Dear ramesh:

It is widely used in modern digital modem to resample without going to analog domain. All can be done digitally.

All the tricks lies in the basic formula:

y(t)=sum{x(m)h(t-mT)} ; T is your sample period.

Use a low pass filter transfer function for h. Then you get data sample at arbitrary time.


regards

 

[ramesh]

polynomial decimation filter implementation

Dear dll_embed

Can you explain little more for the above case, to convert 100MHz sampled data to 90MHz please?

 

[dll_embed]

interpolation and decimation of digital signals

Dear ramesh:

From digital filter theory we know that we can recover a bandwidth limited signal from its sampled discrete data. It is governed by

1. y(t)=sum(x(m)h(t-mTs));
To understand it better, we start from an ideal low pass filter whose impulse response is h(t)=sin(pi*t/Ts)/(pi*t/Ts).

In this case, the Ts is 10ns;

Now we want to resample the y(t) at 90M. So use a NCO at 1/90M interval, we'll calculate the y(t) use equation 1. Then it becomes:

2. y(Ti)=sum(x(m)h(Ti-mTs));

So from 2 we can get y(Ti) (which is 90M sampled). In practice we can use a simpler polynomial based filter. And the result is not bad.

regards

 

[tigger]

fractional polyphase decimator

Most answers above are addressing sample rate conversion, which is somehow different from my original question, but the two are closely related.

For sample rate conversion, one can use NCO or PLL to generate another clock and simply use it to re-sample the input data.

What I intend to do is to use ONLY ONE clock and generate interpolated/decimated output. The application is to restore analog jitters etc. For example, the analog input has embedded sync pulses (start of frame). Since there are fixed number of samples per frame, the time interval between two sync pulses (or frame pulses) should be fixed. However, due to jitters and other reasons, the time intervals change from frame to frame in the analog input. Therefore the task of the DSP block is to interpolate/decimate the A/D data and output fixed number of samples between two sync pulses. Since the DSP block can only use one clock, I don't have the luxury of using PLL, nor can I use NCO because there is no higher frequency available. Does anyone know how to do this? Thanks!

 

[dll_embed]

fractional decimation filter

I don't think it is possible to generate a 90M signal by a single 100M clock. It seems it violates Niquest law. But maybe i understand your question wrongly or some genius has a great idea.

regards

 

[Aoxomox]

interpolation decimation filter design

You need not to transform your intermediate signal to 900 MHz and the devide it back.

Take 100 MHz devide by 10, build up VCO and devide signal by 9. then compare both signals and make a PLL loop. the VCO will be stable when 90MHz/9 == 100MHz/10 are equal.

 

[ramesh]

decimator fractional

What I intend to do is to use ONLY ONE clock and generate interpolated/decimated output. ............
...................
I don't have the luxury of using PLL, nor can I use NCO because there is no higher frequency available. Does anyone know how to do this? Thanks!

Using only one clock and not having the luxury of using PLL Aoxomox's suggestion (which is good) may be of no use then!

 

[tigger]

nco sample rate converter clock

Let me try to explain the problem once again and hopefully it'll be clear this time. There is an analog signal with embedded sync pulses. The A/D converter takes the analog signal and outputs digital data at 100MHz fixed rate. The sync pulses are 1us apart, so there should be 100 samples between two sync pulses. However, due to jitters etc. the number varies from 90 to 110. How do you design a block such that it always outputs 100 samples between to sync pulses. You can't simply drop extra data or pad dummy data -- you have to decimate or interpolate. Also 100MHz is the only clock that is available.

 

[ramesh]

decimation filter implementation

Hi tigger

The problem is now different. For this synchronise your 1MHz sync pluses(1us apart) using a PLL with 100MHz VCXO (voltage controlled crystal oscillator). Use the VCXO ouput to sample the analog signal.

 

[divan]

interpolate decimate

... For this synchronise your 1MHz sync pluses(1us apart) using a PLL with 100MHz VCXO (voltage controlled crystal oscillator). Use the VCXO ouput to sample the analog signal.

Seems this may not be so helpfull, because will not provide a real-time compensation but after PLLL lock time passed only. Of cource need to try lock sample rate to the sync but think u still need resampling only.

 

[gouthamnvaidhya]

Re: Fractional interpolation/decimation filter implementatio

Hi,
Correct me if i am wrong.

The Question is : Conversion of 100MSPS to 90 MSPS (MSPS = MHz)
This can be done by 9/10 (Not 10/9) => 100 *0.9 = 90 MSPS
So following is the process that one needs to follow.
1) Decimation by 10 => 100/10 = 10 MSPS
2) Interpolation by 9 => 10 * 9 = 90 MSPS
Note: Make sure that the Bandwidth of the input data sample is within 5MHz(10MSPS Nyquist rate Fs = Fmax*2)

So guys tell me where is the question of oversampling?
That is 900 MSPS !!!. (Correct me if I am wrong)

In Xilinx they provide fractional interpolator and decimator in the FIR filter Core.
You can use that to achive the rate u r looking for.

Regards,
Goutham