Fractional divide by counter documents

[ASIC_intl]

Can anyone help me with documents to learn about designing divide by 4.5, 5/6, 1.5etc counters. Preferably a general document which states designing fractional divide by counters in general will be helpful.

 

[rca]

what do you mean divider counter? do you mean clock division (lower frequency) ? or processing data division?

 

[ASIC_intl]

By divide by , I mean division of clock frequency so that a clock of lesser frequency is generated.

 

[rca]

I have written some code to divide by step of 1/8, this code only generate a gated clock enable condition to reduce the master clock speed. Then the duty cycle is not 50%.
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/ : 16 system clock
_/_/_/_/_/_/_/__/_/_/_/_/_/_/__ : 14 system clock if I divided by 1/8, I lost 1 pulse each 8 pulses.

So for you case of 5/6, you could made the same as mine but with decrement of 6 instead 8:
ENTITY clk_divider IS
PORT(
...
-- prescaler value
div_clk_prescale : IN std_logic_vector( 9 DOWNTO 0); -- div clock prescaler
...
);
END;

ARCHITECTURE A OF clk_divider IS
SIGNAL div_clk_cnt : std_logic_vector(10 DOWNTO 0); -- counter for div clock generator
SIGNAL next_div_clk_cnt : std_logic_vector(10 DOWNTO 0); -- counter+1 for div clock generator
SIGNAL div_en : std_logic;

-- ##############################################################################
-- prescaler for div - USER - Slow clocks
-- ##############################################################################
-- prescale state values for slow_clk / USERCLK / div_clk
p_presc: PROCESS(nreset,sys_clk)
BEGIN
IF nreset='0' THEN
div_clk_cnt <= (OTHERS =>'0');
ELSIF sys_clk'event AND sys_clk='1' THEN
-- flip-flop for div clock
IF use_prescaler_div_clk='1' THEN
div_clk_cnt <= next_div_clk_cnt;
ELSE
div_clk_cnt <= (OTHERS =>'0');
END IF;
END IF;
END PROCESS;

-- ##############################################################################
-- div clock prescaler => enable
-- ##############################################################################
-- combinatorial signal definitions use to disabled the counter
p_use_prescale_div_clk: PROCESS(div_clk_prescale)
BEGIN
IF div_clk_prescale=X"00" & "00" THEN -- no prescaling
use_prescaler_div_clk<='0';
ELSE
use_prescaler_div_clk<='1';
END IF;
END PROCESS;

-- counter & control the signal to generate the enable
p_comd_div_clk: PROCESS(use_prescaler_div_clk,div_clk_prescale,div_clk_cnt)
VARIABLE v_next_presc: std_logic_vector(10 DOWNTO 0);
BEGIN
IF use_prescaler_div_clk='0' THEN -- no prescaling
v_next_presc := (OTHERS=>'0');
div_en <='1';
ELSE
IF SIGNED(div_clk_cnt)>=SIGNED('0' & div_clk_prescale) THEN
v_next_presc:=UNSIGNED(div_clk_cnt) - 8;
div_en<='0';
ELSE
v_next_presc:=UNSIGNED(div_clk_cnt) + UNSIGNED('0'&div_clk_prescale);
div_en<='1';
END IF;
END IF;
next_div_clk_cnt<=v_next_presc;
END PROCESS;

clk_divider_en.div <= div_en;