Fractional clock divider

Code Verilog - [expand]
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// credit: Adapted from [url]https://zipcpu.com/blog/2017/06/02/generating-timing.html[/url]
 
module baud_generator(clk, baud_out);     // we are obtaining baud_out = 9600bps = clk/5000 where clk = 48MHz
 
input clk;
output baud_out;
 
reg ck_stb;
reg[31:0] counter = 0;
 
always @(posedge clk)
    {ck_stb, counter} <= counter + 858993;  // (2^32)/5000 ~= 858993 , actual baudrate = 9599.9949bps
                        // baud_out has a period of (1/9599.9949bps) or 104167ns
assign baud_out = ck_stb;
 
endmodule

Code Verilog - [expand]
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`timescale 1ps/1ps
 
module baud_generator_tb;
  reg clk;
  wire baud_out;
 
    baud_generator BG1
    (
      .clk(clk),
      .baud_out(baud_out)
    );
 
    initial
    begin
        $dumpfile("baud_generator.vcd");
        $dumpvars(0, baud_generator_tb);
 
            clk = 0;    
 
        #1000000000 $finish;
    end
 
  always #10417 clk = !clk;  // 48Mhz has a clock period of (20833/2)ps
endmodule