Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

FPGA VGA Glitch Problem

Status
Not open for further replies.

nmcgnyksl

Newbie level 1
Joined
Jul 1, 2014
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
13
Hello everyone,
I am trying to create a game on FPGA and to do so I need to use VGA. However there are glitches on the screen and I don't know what causes this problem. Help is much appriciated. I am posting the screen photo and the scynhonization code. I am using 640x480 60Hz. Thank you.
(Sorry for my english if there is any problem)

20150509_094845.jpg


Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
parameter hpix = 800;    // total horizontal pixels
parameter vpix = 525;   // total vertical pixels
parameter hlow = 96;        // first low signal of horizontal
parameter hbp = 144;        // end of back porch
parameter hfp = 784;        // start of front porch
parameter vlow = 2;     // first low vertical
parameter vbp = 35;     // back porch end
parameter vfp = 515;        // front porch start
 
    always @(posedge sclk)  //counting hreg vreg
                    begin
                        if (hreg < hpix-1)
                              hreg <= hreg+1;
                        else 
                           begin
                             hreg <=0;
                            if (vreg < vpix-1)
                        vreg <= vreg+1;
                        else 
                         vreg <=0;
                           end
                if(hreg>142)   //  generating creating screen map for sh<640 sv<480
                 sh <= hreg-143;
                else
                 sh <= hreg+657;
                 if(vreg>31)
                 sv <= vreg-32;
                else
                 sv <= vreg+491;
                    end
 
assign hsync = (hreg<hlow) ? 0:1;
assign vsync = (vreg<vlow) ? 0:1;

 
Last edited by a moderator:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top