TuAtAu
Advanced Member level 4
[SOLVED][FPGA]Using RAM Block as CACHE (VHDL)
Hi, I am facing 2 problems, need some advice.
1. I have 2MB BRAM , can I sperate them 1MB to instructions 1MB to data for my softcore cache?
or it must use it in full 2MB?
2. If it is able to do it, how to do it in VHDL. I dont want to use coregen. I want to learn how to program the BRAM by using VHDL.. any reference or details?
Thanks in advance!
APPENDIX:
Model: Xilinx Spartan-3A DSP, XC3SD3400A-4FGG676C
• DSP Performance: 32 GMACS
• Maximum DSP frequency: 250 MHz
• Block RAM: 2,268 Kb
• Logic cells: 53,712
• Speed: 213 × 622+ Mbps LVDS pairs
Hi, I am facing 2 problems, need some advice.
1. I have 2MB BRAM , can I sperate them 1MB to instructions 1MB to data for my softcore cache?
or it must use it in full 2MB?
2. If it is able to do it, how to do it in VHDL. I dont want to use coregen. I want to learn how to program the BRAM by using VHDL.. any reference or details?
Thanks in advance!
APPENDIX:
Model: Xilinx Spartan-3A DSP, XC3SD3400A-4FGG676C
• DSP Performance: 32 GMACS
• Maximum DSP frequency: 250 MHz
• Block RAM: 2,268 Kb
• Logic cells: 53,712
• Speed: 213 × 622+ Mbps LVDS pairs
Last edited: